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Yuan Taur - Publications

Affiliations: 
Electrical Engineering (Applied Physics) University of California, San Diego, La Jolla, CA 
Area:
Electronics and Electrical Engineering
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97 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Ren Z, Taur Y. Non-GCA modeling of near threshold I-V characteristics of DG MOSFETs Solid-State Electronics. 166: 107766. DOI: 10.1016/J.Sse.2020.107766  0.737
2019 Kavrik MS, Bostwick A, Rotenberg E, Tang K, Thomson E, Aoki T, Fruhberger B, Taur Y, McIntyre PC, Kummel AC. Understanding the Mechanism of Electronic Defects Suppression Enabled by Non-Idealities in Atomic Layer Deposition. Journal of the American Chemical Society. PMID 31779305 DOI: 10.1021/Jacs.9B06640  0.314
2019 Kavrik MS, Ercius P, Cheung J, Tang K, Wang Q, Fruhberger B, Kim MJ, Taur Y, McIntyre PC, Kummel AC. Engineering high-k/SiGe interface with ALD oxide for selective GeOx reduction. Acs Applied Materials & Interfaces. PMID 30938163 DOI: 10.1021/Acsami.8B22362  0.332
2019 Taur Y, Choi W, Zhang J, Su M. A Non-GCA DG MOSFET Model Continuous into the Velocity Saturation Region Ieee Transactions On Electron Devices. 66: 1160-1166. DOI: 10.1109/Ted.2019.2894685  0.488
2018 Kavrik MS, Thomson E, Chagarov E, Tang K, Ueda ST, Hou V, Aoki T, Kim MJ, Fruhberger B, Taur Y, McIntyre PC, Kummel AC. Ultra-Low defect density at sub-0.5 nm HfO2/SiGe interfaces via selective oxygen scavenging. Acs Applied Materials & Interfaces. PMID 30073827 DOI: 10.1021/Acsami.8B06547  0.38
2018 Pandey N, Lin H, Nandi A, Taur Y. Modeling of Short-Channel Effects in DG MOSFETs: Green’s Function Method Versus Scale Length Model Ieee Transactions On Electron Devices. 65: 3112-3119. DOI: 10.1109/Ted.2018.2845875  0.521
2018 Taur Y, Lin H. Modeling of DG MOSFET $I$ – $V$ Characteristics in the Saturation Region Ieee Transactions On Electron Devices. 65: 1714-1720. DOI: 10.1109/Ted.2018.2818943  0.557
2018 Parihar MS, Lee KH, Park HJ, Lacord J, Martinie S, Barbé J, Xu Y, El Dirani H, Taur Y, Cristoloveanu S, Bawedin M. Insight into carrier lifetime impact on band-modulation devices Solid-State Electronics. 143: 41-48. DOI: 10.1016/J.Sse.2017.12.007  0.376
2018 Cristoloveanu S, Lee K, Parihar M, El Dirani H, Lacord J, Martinie S, Le Royer C, Barbe J, Mescot X, Fonteneau P, Galy P, Gamiz F, Navarro C, Cheng B, Duan M, ... ... Taur Y, et al. A review of the Z 2 -FET 1T-DRAM memory: Operation mechanisms and key parameters Solid-State Electronics. 143: 10-19. DOI: 10.1016/J.Sse.2017.11.012  0.306
2017 Wu J, Taur Y. An All-Region I–V Model for 1-D Nanowire MOSFETs Ieee Transactions On Nanotechnology. 16: 1062-1066. DOI: 10.1109/Tnano.2017.2745447  0.538
2017 Lin H, Taur Y. Effect of Source–Drain Doping on Subthreshold Characteristics of Short-Channel DG MOSFETs Ieee Transactions On Electron Devices. 64: 4856-4860. DOI: 10.1109/Ted.2017.2766920  0.426
2017 Xie Q, Wang Z, Taur Y. Analysis of Short-Channel Effects in Junctionless DG MOSFETs Ieee Transactions On Electron Devices. 64: 3511-3514. DOI: 10.1109/Ted.2017.2716969  0.467
2017 Taur Y, Lacord J, Parihar MS, Wan J, Martinie S, Lee K, Bawedin M, Barbe J, Cristoloveanu S. A comprehensive model on field-effect pnpn devices (Z 2 -FET) Solid-State Electronics. 134: 1-8. DOI: 10.1016/J.Sse.2017.05.004  0.519
2017 El Dirani H, Lee K, Parihar M, Lacord J, Martinie S, Barbe J, Mescot X, Fonteneau P, Broquin J, Ghibaudo G, Galy P, Gamiz F, Taur Y, Kim Y, Cristoloveanu S, et al. Ultra-low power 1T-DRAM in FDSOI technology Microelectronic Engineering. 178: 245-249. DOI: 10.1016/J.Mee.2017.05.047  0.32
2016 Wu J, Taur Y. Reduction of TFET OFF-Current and Subthreshold Swing by Lightly Doped Drain Ieee Transactions On Electron Devices. 63: 3342-3345. DOI: 10.1109/Ted.2016.2577589  0.47
2016 Taur Y, Wu J, Min J. A Short-Channel $I$ – $V$ Model for 2-D MOSFETs Ieee Transactions On Electron Devices. 63: 2550-2555. DOI: 10.1109/Ted.2016.2547949  0.551
2016 Wu J, Taur Y. A Continuous Semianalytic Current Model for DG and NW TFETs Ieee Transactions On Electron Devices. 63: 841-847. DOI: 10.1109/Ted.2015.2509468  0.537
2016 Taur Y, Wu J, Min J. Dimensionality dependence of TFET performance down to 0.1 v supply voltage Ieee Transactions On Electron Devices. 63: 877-880. DOI: 10.1109/Ted.2015.2508282  0.403
2016 Taur Y, Wu J. Examination of Two-Band $E(k)$ Relations for Band-to-Band Tunneling Ieee Transactions On Electron Devices. 63: 869-872. DOI: 10.1109/Ted.2015.2505505  0.32
2016 Gu S, Min J, Taur Y, Asbeck PM. Characterization of interface defects in ALD Al2O3/p-GaSb MOS capacitors using admittance measurements in range from kHz to GHz Solid-State Electronics. 118: 18-25. DOI: 10.1016/J.Sse.2016.01.001  0.331
2015 Wu J, Min J, Taur Y. Short-Channel Effects in Tunnel FETs Ieee Transactions On Electron Devices. 62: 3019-3024. DOI: 10.1109/Ted.2015.2458977  0.461
2015 Taur Y, Wu J, Min J. An Analytic Model for Heterojunction Tunnel FETs With Exponential Barrier Ieee Transactions On Electron Devices. 62: 1399-1404. DOI: 10.1109/Ted.2015.2407695  0.532
2015 Taur Y, Chen H, Xie Q, Ahn J, McIntyre PC, Lin D, Vais A, Veksler D. A Unified Two-Band Model for Oxide Traps and Interface States in MOS Capacitors Ieee Transactions On Electron Devices. 62: 813-820. DOI: 10.1109/Ted.2015.2389805  0.622
2015 Min J, Wu J, Taur Y. Analysis of Source Doping Effect in Tunnel FETs With Staggered Bandgap Ieee Electron Device Letters. 36: 1094-1096. DOI: 10.1109/Led.2015.2466676  0.396
2014 Chen H, Ahn J, McIntyre PC, Taur Y. Effects of oxide thickness and temperature on dispersions in InGaAs MOS C-V characteristics Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena. 32: 03D111. DOI: 10.1116/1.4864618  0.564
2014 Chen HP, Veksler D, Bersuker G, Taur Y. Modeling illumination effects on n- and p-Type InGaAs MOS at room and low temperatures Ieee Transactions On Electron Devices. 61: 1483-1487. DOI: 10.1109/Ted.2014.2312329  0.574
2014 Dou C, Lin D, Vais A, Ivanov T, Chen HP, Martens K, Kakushima K, Iwai H, Taur Y, Thean A, Groeseneken G. Determination of energy and spatial distribution of oxide border traps in In0.53Ga0.47As MOS capacitors from capacitance-voltage characteristics measured at various temperatures Microelectronics Reliability. 54: 746-754. DOI: 10.1016/J.Microrel.2013.12.023  0.551
2013 Chen H, Ahn J, McIntyre PC, Taur Y. Comparison of Bulk-Oxide Trap Models: Lumped Versus Distributed Circuit Ieee Transactions On Electron Devices. 60: 3920-3924. DOI: 10.1109/Ted.2013.2281298  0.627
2013 Xie Q, Lee C, Xu J, Wann C, Sun JY, Taur Y. Comprehensive Analysis of Short-Channel Effects in Ultrathin SOI MOSFETs Ieee Transactions On Electron Devices. 60: 1814-1819. DOI: 10.1109/Ted.2013.2255878  0.461
2013 Taur Y, Chen H, Yuan Y, Yu B. Comments to “A Distributive-Transconductance Model for Border Traps in III-V/High-k MOS Capacitors” Ieee Electron Device Letters. 34: 1343-1344. DOI: 10.1109/Led.2013.2278097  0.622
2013 Chen H, Yuan Y, Yu B, Chang C, Wann C, Taur Y. Re-examination of the extraction of MOS interface-state density by C–V stretchout and conductance methods Semiconductor Science and Technology. 28: 085008. DOI: 10.1088/0268-1242/28/8/085008  0.559
2013 Yu B, Yuan Y, Chen H, Ahn J, McIntyre P, Taur Y. Effect and extraction of series resistance in Al2O3-InGaAs MOS with bulk-oxide trap Electronics Letters. 49: 492-493. DOI: 10.1049/El.2013.0433  0.323
2012 Chen HP, Yuan Y, Yu B, Ahn J, McIntyre PC, Asbeck PM, Rodwell MJW, Taur Y. Interface-State Modeling of Al 2O 3-InGaAs MOS From Depletion to Inversion Ieee Transactions On Electron Devices. DOI: 10.1109/Ted.2012.2205255  0.646
2012 Yuan Y, Yu B, Ahn J, McIntyre PC, Asbeck PM, Rodwell MJW, Taur Y. A distributed bulk-oxide trap model for Al 2O 3 InGaAs MOS devices Ieee Transactions On Electron Devices. 59: 2100-2106. DOI: 10.1109/Ted.2012.2197000  0.465
2012 Xie Q, Xu J, Taur Y. Review and Critique of Analytic Models of MOSFET Short-Channel Effects in Subthreshold Ieee Transactions On Electron Devices. 59: 1569-1579. DOI: 10.1109/Ted.2012.2191556  0.482
2012 Taur Y, Chen H, Wang W, Lo S, Wann C. On–Off Charge–Voltage Characteristics and Dopant Number Fluctuation Effects in Junctionless Double-Gate MOSFETs Ieee Transactions On Electron Devices. 59: 863-866. DOI: 10.1109/Ted.2011.2181392  0.664
2011 Chen HP, Lee VC, Ohoka A, Xiang J, Taur Y. Modeling and design of ferroelectric MOSFETs Ieee Transactions On Electron Devices. 58: 2401-2405. DOI: 10.1109/Ted.2011.2155067  0.657
2011 Yuan Y, Wang L, Yu B, Shin B, Ahn J, McIntyre PC, Asbeck PM, Rodwell MJW, Taur Y. A distributed model for border traps in Al2O3 - InGaAs MOS devices Ieee Electron Device Letters. 32: 485-487. DOI: 10.1109/Led.2011.2105241  0.463
2010 Asbeck PM, Wang L, Gu S, Taur Y, Yu ET. Tunneling MOSFETs based on III-V staggered heterojunctions Materials Research Society Symposium Proceedings. 1252: 3-9. DOI: 10.1557/Proc-1252-I02-04  0.464
2010 Asbeck P, Wang L, Gu S, Taur Y, Yu E. Tunneling MOSFETs Based on III-V Staggered Heterojunctions Mrs Proceedings. 1252. DOI: 10.1557/PROC-1252-I02-04  0.359
2010 Song J, Yuan Y, Yu B, Xiong W, Taur Y. Compact Modeling of Experimental n- and p-Channel FinFETs Ieee Transactions On Electron Devices. 57: 1369-1374. DOI: 10.1109/Ted.2010.2047067  0.783
2010 Wang L, Yu E, Taur Y, Asbeck P. Design of Tunneling Field-Effect Transistors Based on Staggered Heterojunctions for Ultralow-Power Applications Ieee Electron Device Letters. 31: 431-433. DOI: 10.1109/Led.2010.2044012  0.375
2010 Xie Q, Xu J, Ren T, Taur Y. A 2D analytical model for SCEs in MOSFETs with high-kgate dielectric Semiconductor Science and Technology. 25: 035012. DOI: 10.1088/0268-1242/25/3/035012  0.527
2010 Wang L, Asbeck PM, Taur Y. Self-consistent 1-D Schrödinger-Poisson solver for III-V heterostructures accounting for conduction band non-parabolicity Solid-State Electronics. 54: 1257-1262. DOI: 10.1016/J.Sse.2010.06.018  0.444
2010 Wang W, Lu H, Song J, Lo S, Taur Y. Compact modeling of quantum effects in symmetric double-gate MOSFETs Microelectronics Journal. 41: 688-692. DOI: 10.1016/J.Mejo.2010.05.007  0.793
2009 Wang L, Yu B, Asbeck PM, Taur Y, Rodwell M. Performance comparison of scaled III-V and Si ballistic nanowire MOSFETs International Journal of High Speed Electronics and Systems. 19: 15-22. DOI: 10.1142/S0129156409006059  0.441
2009 Yu B, Yuan Y, Song J, Taur Y. A Two-Dimensional Analytical Solution for Short-Channel Effects in Nanowire MOSFETs Ieee Transactions On Electron Devices. 56: 2357-2362. DOI: 10.1109/Ted.2009.2028048  0.794
2009 Song J, Yu B, Xiong W, Taur Y. Gate-Length-Dependent Strain Effect in n- and p-Channel FinFETs Ieee Transactions On Electron Devices. 56: 533-536. DOI: 10.1109/Ted.2008.2011840  0.755
2009 Singisetti U, Wistey MA, Burek GJ, Baraskar AK, Thibeault BJ, Gossard AC, Rodwell MJW, Shin B, Kim EJ, McIntyre PC, Yu B, Yuan Y, Wang D, Taur Y, Asbeck P, et al. In0.53Ga0.47As Channel MOSFETs with self-aligned InAs source/drain formed by MEE regrowth Ieee Electron Device Letters. 30: 1128-1130. DOI: 10.1109/Led.2009.2031304  0.403
2009 Yuan Y, Yu B, Song J, Taur Y. An analytic model for threshold voltage shift due to quantum confinement in surrounding gate MOSFETs with anisotropic effective mass Solid-State Electronics. 53: 140-144. DOI: 10.1016/J.Sse.2008.10.010  0.77
2008 Yu B, Song J, Yuan Y, Lu W, Taur Y. A Unified Analytic Drain–Current Model for Multiple-Gate MOSFETs Ieee Transactions On Electron Devices. 55: 2157-2163. DOI: 10.1109/Ted.2008.926228  0.823
2008 Yu B, Wang L, Yuan Y, Asbeck PM, Taur Y. Scaling of nanowire transistors Ieee Transactions On Electron Devices. 55: 2846-2858. DOI: 10.1109/Ted.2008.2005163  0.456
2008 Lu H, Yu B, Taur Y. A unified charge model for symmetric double-gate and surrounding-gate MOSFETs Solid-State Electronics. 52: 67-72. DOI: 10.1016/J.Sse.2007.06.018  0.826
2007 Yu B, Lu H, Liu M, Taur Y. Explicit Continuous Models for Double-Gate and Surrounding-Gate MOSFETs Ieee Transactions On Electron Devices. 54: 2715-2722. DOI: 10.1109/Ted.2007.904410  0.816
2007 Yu B, Lu W, Lu H, Taur Y. Analytic Charge Model for Surrounding-Gate MOSFETs Ieee Transactions On Electron Devices. 54: 492-496. DOI: 10.1109/Ted.2006.890264  0.781
2007 Lu H, Lu W, Taur Y. Effect of body doping on double-gate MOSFET characteristics Semiconductor Science and Technology. 23: 015006. DOI: 10.1088/0268-1242/23/1/015006  0.793
2007 Cai M, Liu M, Taur Y. Simulation study of the noise figure of nanometer-gate nMOS transistors near the scaling limit Solid-State Electronics. 51: 667-673. DOI: 10.1016/J.Sse.2007.02.014  0.307
2006 Liu M, Cai M, Yu B, Taur Y. Effect of Gate Overlap and Source/Drain Doping Gradient on 10-nm CMOS Performance Ieee Transactions On Electron Devices. 53: 3146-3149. DOI: 10.1109/Ted.2006.885103  0.675
2006 Lu H, Taur Y. An analytic potential model for symmetric and asymmetric DG MOSFETs Ieee Transactions On Electron Devices. 53: 1161-1168. DOI: 10.1109/Ted.2006.872093  0.831
2006 Lu W, Taur Y. On the scaling limit of ultrathin SOI MOSFETs Ieee Transactions On Electron Devices. 53: 1137-1141. DOI: 10.1109/Ted.2006.871879  0.327
2005 Sleva S, Taur Y. The Influence of Source and Drain Junction Depth on the Short-Channel Effect in MOSFETs Ieee Transactions On Electron Devices. 52: 2814-2816. DOI: 10.1109/Ted.2005.859614  0.469
2004 Liang X, Taur Y. A 2-D Analytical Solution for SCEs in DG MOSFETs Ieee Transactions On Electron Devices. 51: 1385-1391. DOI: 10.1109/Ted.2004.832707  0.713
2004 Taur Y, Liang X, Wang W, Lu H. A Continuous, Analytic Drain-Current Model for DG MOSFETs Ieee Electron Device Letters. 25: 107-109. DOI: 10.1109/Led.2003.822661  0.815
2002 Taur Y. CMOS design near the limit of scaling Ibm Journal of Research and Development. 46: 213-222. DOI: 10.1147/Rd.462.0213  0.327
2002 Floyd BA, Shi L, Taur Y, Lagnado I. A 23.8-GHz SOI CMOS tuned amplifier Ieee Transactions On Microwave Theory and Techniques. 50: 2193-2196. DOI: 10.1109/Tmtt.2002.802334  0.312
2002 Rosenthal PA, Taur Y, Yu ET. Direct measurement and characterization of n+ superhalo implants in a 120 nm gate-length Si metal–oxide–semiconductor field-effect transistor using cross-sectional scanning capacitance microscopy Applied Physics Letters. 81: 3993-3995. DOI: 10.1063/1.1522819  0.384
2002 Taur Y. Transistors and IC design Advances in Computers. 55: 237-279. DOI: 10.1016/S0065-2458(01)80031-0  0.3
2002 Frank DJ, Taur Y. Design considerations for CMOS near the limits of scaling Solid-State Electronics. 46: 315-320. DOI: 10.1016/S0038-1101(01)00102-2  0.391
2001 Taur Y. Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs Ieee Transactions On Electron Devices. 48: 2861-2869. DOI: 10.1109/16.974719  0.565
2000 Taur Y. An analytical solution to a double-gate MOSFET with undoped body Ieee Electron Device Letters. 21: 245-247. DOI: 10.1109/55.841310  0.525
2000 Taur Y. MOSFET channel length: extraction and interpretation Ieee Transactions On Electron Devices. 47: 160-170. DOI: 10.1109/16.817582  0.47
1999 Lo S-, Buchanan DA, Taur Y. Modeling and characterization of quantization, polysilicon depletion, and direct tunneling effects in MOSFETs with ultrathin oxides Ibm Journal of Research and Development. 43: 327-337. DOI: 10.1147/Rd.433.0327  0.47
1999 Taur Y. The incredible shrinking transistor Ieee Spectrum. 36: 25-29. DOI: 10.1109/6.774961  0.338
1998 Frank DJ, Taur Y, Wong HSP. Generalized scale length for two-dimensional effects in MOSFET's Ieee Electron Device Letters. 19: 385-387. DOI: 10.1109/55.720194  0.39
1998 Taur Y, Ning TH. FEOL technology trend Materials Chemistry and Physics. 52: 191-199. DOI: 10.1016/S0254-0584(97)02029-4  0.36
1998 Philip Wong H, Taur Y, Frank DJ. Discrete random dopant distribution effects in nanometer-scale MOSFETs Microelectronics Reliability. 38: 1447-1456. DOI: 10.1016/S0026-2714(98)00053-5  0.427
1997 Wann C, Assaderaghi F, Shi L, Chan K, Cohen S, Hovel H, Jenkins K, Lee Y, Sadana D, Viswanathan R, Wind S, Taur Y. High-performance 0.07-μm CMOS with 9.5-ps gate delay and 150 GHz f/sub T/ Ieee Electron Device Letters. 18: 625-627. DOI: 10.1109/55.644091  0.361
1997 Lo SH, Buchanan DA, Taur Y, Wang W. Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's Ieee Electron Device Letters. 18: 209-211. DOI: 10.1109/55.568766  0.415
1995 Wind SJ, Taur Y, Mii Y, Frank DJ, Wong H, Buchanan DA, Rishton SA, Bucchignano JJ, Lii Y, Jenkins KA. Probing the Limits of Silicon-Based Nanoelectronics Mrs Proceedings. 380. DOI: 10.1557/Proc-380-179  0.362
1995 Wind SJ, Taur Y, Lee YH, Mii Y, Viswanathan RG, Bucchignano JJ, Pomerene AT, Sicina RM, Milkove KR, Stiebritz JW, Roy RA, Hu CK, Manny MP, Cohen S, Chen W. Lithography and fabrication processes for sub-100 nm scale complementary metal-oxide semiconductor Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures. 13: 2688-2695. DOI: 10.1116/1.588050  0.397
1995 Taur Y, Mii Y, Logan R, Wong H. On "effective channel length" in 0.1-μm MOSFETs Ieee Electron Device Letters. 16: 136-138. DOI: 10.1109/55.372493  0.398
1994 Mii Y, Rishton S, Taur Y, Kern D, Lii T, Lee K, Jenkins KA, Quinlan D, Brown T, Danner D, Sewell F, Polcari M. Experimental High Performance Sub-0.1 μm Channel nMOSFET's Ieee Electron Device Letters. 15: 28-30. DOI: 10.1109/55.289472  0.39
1994 Hsu CC-, Wen D, Wordeman MR, Taur Y, Ning TH. A comprehensive study of hot-carrier instability in p- and n-type poly-Si gated MOSFET's Ieee Transactions On Electron Devices. 41: 675-680. DOI: 10.1109/16.285016  0.404
1994 Buchanan DA, DiMaria DJ, Chang CA, Taur Y. Defect generation in 3.5 nm silicon dioxide films Applied Physics Letters. 65: 1820-1822. DOI: 10.1063/1.112854  0.305
1993 Taur Y, Cohen S, Wind S, Lii T, Hsu C, Quinlan D, Chang CA, Buchanan D, Agnello P, Mii YJ, Reeves C, Acovic A, Kesan V. Experimental 0.1-um p-Channel MOSFET with p+-Polysilicon Gate on 35-A Gate Oxide Ieee Electron Device Letters. 14: 304-306. DOI: 10.1109/55.215206  0.379
1993 Taur Y, Hsu C, Wu B, Kiehl R, Davari B, Shahidi G. Saturation transconductance of deep-submicron-channel MOSFETs Solid-State Electronics. 36: 1085-1087. DOI: 10.1016/0038-1101(93)90185-S  0.365
1992 Hsu CCH, Acovic A, Dori L, Wu B, Lii T, Quinlan D, DiMaria D, Taur Y, Wordeman M, Ning T. A High Speed, Low Power P-Channel Flash EEPROM Using Silicon Rich Oxide as Tunneling Dielectric The Japan Society of Applied Physics. DOI: 10.7567/Ssdm.1992.Pa2-2  0.348
1992 Warnock J, Shahidi G, Dasvari B, Wu B, Taur Y, Wong C, Jenkins K, Chen C. BiCMOS technology with 60 GHz n-p-n bipolar and 0.25 mu m CMOS Ieee Electron Device Letters. 13: 578-580. DOI: 10.1109/55.192841  0.355
1992 Taur Y, Zicherman DS, Lombardi DR, Restle PJ, Hsu CH, Hanafi HI, Wordeman MR, Davari B, Shahidi GG. A New “Shift and Ratio” Method for MOSFET Channel-Length Extraction Ieee Electron Device Letters. 13: 267-269. DOI: 10.1109/55.145049  0.419
1992 Davari B, Chang W, Petrillo K, Wong C, Moy D, Taur Y, Wordeman M, Sun J, Hsu C, Polcari M. A high-performance 0.25- mu m CMOS technology. II. Technology Ieee Transactions On Electron Devices. 39: 967-975. DOI: 10.1109/16.127490  0.383
1992 Chang W, Davari B, Wordeman M, Taur Y, Hsu C, Rodriguez M. A high-performance 0.25- mu m CMOS technology. I. Design and characterization Ieee Transactions On Electron Devices. 39: 959-966. DOI: 10.1109/16.127489  0.36
1989 Wong C, Piccirillo J, Bhattacharyya A, Taur Y, Hanafi H. Sidewall oxidation of polycrystalline-silicon gate Ieee Electron Device Letters. 10: 420-422. DOI: 10.1109/55.34729  0.412
1987 Taur Y, Sun JY-, Moy D, Wang LK, Davari B, Klepner SP, Ting C. Source—Drain contact resistance in CMOS with self-aligned TiSi 2 Ieee Transactions On Electron Devices. 34: 575-580. DOI: 10.1109/T-Ed.1987.22965  0.327
1987 Sun JY-, Taur Y, Dennard RH, Klepner SP. Submicrometer-channel CMOS for low-temperature operation Ieee Transactions On Electron Devices. 34: 19-27. DOI: 10.1109/T-Ed.1987.22881  0.466
1986 Lai FJ, Wang LK, Taur Y, Sun JY-, Petrillo KE, Chicotka SK, Petrillo EJ, Polcari MR, Bucelot TJ, Zicherman DS. A highly latchup-immune 1-µm CMOS technology fabricated with 1-MeV ion implantation and self-aligned TiSi 2 Ieee Transactions On Electron Devices. 33: 1308-1320. DOI: 10.1109/T-Ed.1986.22664  0.403
1985 Taur Y, Hu GJ, Dennard RH, Terman LM, Ting C, Petrillo KE. A self-aligned 1-µm-channel CMOS technology with retrograde n-well and thin epitaxy Ieee Transactions On Electron Devices. 32: 203-209. DOI: 10.1109/T-Ed.1985.21930  0.398
1985 Taur Y, Hu GJ, Dennard RH, Terman LM, Ting CY, Petrillo KE. A Self-Aligned 1-μm-Channel CMOS Technology with Retrograde n-Well and Thin Epitaxy Ieee Journal of Solid-State Circuits. 20: 123-129. DOI: 10.1109/Jssc.1985.1052284  0.365
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