| Year |
Citation |
Score |
| 2020 |
Park H, Colinge J, Cristoloveanu S, Bawedin M. Persistent Floating‐Body Effects in Fully Depleted Silicon‐On‐Insulator Transistors Physica Status Solidi (a). 217: 1900948. DOI: 10.1002/Pssa.201900948 |
0.421 |
|
| 2014 |
Colinge JP. Multigate transistors: Pushing Moore's law to the limit International Conference On Simulation of Semiconductor Processes and Devices, Sispad. 313-316. DOI: 10.1109/SISPAD.2014.6931626 |
0.381 |
|
| 2013 |
Colinge JP. 3D transistors 2013 International Symposium On Vlsi Technology, Systems and Application, Vlsi-Tsa 2013. DOI: 10.1109/VLSI-TSA.2013.6545628 |
0.361 |
|
| 2013 |
Colinge JP, Dhong SH. Prospective for nanowire transistors Proceedings of the Custom Integrated Circuits Conference. DOI: 10.1109/CICC.2013.6658401 |
0.357 |
|
| 2013 |
Yu R, Nazarov AN, Lysenko VS, Das S, Ferain I, Razavi P, Shayesteh M, Kranti A, Duffy R, Colinge JP. Impact ionization induced dynamic floating body effect in junctionless transistors Solid-State Electronics. 90: 28-33. DOI: 10.1016/j.sse.2013.02.056 |
0.443 |
|
| 2012 |
Ansari L, Fagas G, Colinge JP, Greer JC. A proposed confinement modulated gap nanowire transistor based on a metal (tin). Nano Letters. 12: 2222-7. PMID 22500745 DOI: 10.1021/Nl2040817 |
0.423 |
|
| 2012 |
Hobbs RG, Schmidt M, Bolger CT, Georgiev YM, Fleming P, Morris MA, Petkov N, Holmes JD, Xiu F, Wang KL, Djara V, Yu R, Colinge JP. Resist-substrate interface tailoring for generating high-density arrays of Ge and Bi2Se3 nanowires by electron beam lithography Journal of Vacuum Science and Technology B:Nanotechnology and Microelectronics. 30. DOI: 10.1116/1.4724302 |
0.327 |
|
| 2012 |
Razavi P, Ferain I, Das S, Yu R, Akhavan ND, Colinge JP. Intrinsic gate delay and energy-delay product in junctionless nanowire transistors 2012 13th International Conference On Ultimate Integration On Silicon, Ulis 2012. 125-128. DOI: 10.1109/ULIS.2012.6193373 |
0.401 |
|
| 2012 |
Yu R, Das S, Ferain I, Razavi P, Shayesteh M, Kranti A, Duffy R, Colinge JP. Device design and estimated performance for p-type junctionless transistors on bulk germanium substrates Ieee Transactions On Electron Devices. 59: 2308-2313. DOI: 10.1109/Ted.2012.2202239 |
0.512 |
|
| 2012 |
Colinge JP. Junctionless transistors Imfedk 2012 - 2012 International Meeting For Future of Electron Devices, Kansai. 20-21. DOI: 10.1109/IMFEDK.2012.6218561 |
0.393 |
|
| 2012 |
Goto KI, Yu TH, Wu J, Diaz CH, Colinge JP. Mobility and screening effect in heavily doped accumulation-mode metal-oxide-semiconductor field-effect transistors Applied Physics Letters. 101. DOI: 10.1063/1.4745604 |
0.42 |
|
| 2012 |
Razavi P, Fagas G, Ferain I, Yu R, Das S, Colinge JP. Influence of channel material properties on performance of nanowire transistors Journal of Applied Physics. 111. DOI: 10.1063/1.4729777 |
0.47 |
|
| 2012 |
Park JT, Kim JY, Colinge JP. Negative-bias-temperature-instability and hot carrier effects in nanowire junctionless p-channel multigate transistors Applied Physics Letters. 100: 83504. DOI: 10.1063/1.3688245 |
0.557 |
|
| 2012 |
Akhavan ND, Ferain I, Yu R, Razavi P, Colinge JP. Influence of discrete dopant on quantum transport in silicon nanowire transistors Solid-State Electronics. 70: 92-100. DOI: 10.1016/J.Sse.2011.11.017 |
0.486 |
|
| 2012 |
Ansari L, Feldman B, Fagas G, Colinge JP, Greer JC. Subthreshold behavior of junctionless silicon nanowire transistors from atomic scale simulations Solid-State Electronics. 71: 58-62. DOI: 10.1016/J.Sse.2011.10.021 |
0.453 |
|
| 2012 |
Akhavan ND, Ferain I, Yu R, Razavi P, Colinge JP. Emission and absorption of optical phonons in multigate silicon nanowire MOSFETs Journal of Computational Electronics. 11: 249-265. DOI: 10.1007/S10825-012-0411-1 |
0.398 |
|
| 2011 |
Ferain I, Colinge CA, Colinge JP. Multigate transistors as the future of classical metal-oxide-semiconductor field-effect transistors. Nature. 479: 310-6. PMID 22094690 DOI: 10.1038/Nature10676 |
0.468 |
|
| 2011 |
Tang X, Krzeminski C, Lecavelier des Etangs-Levallois A, Chen Z, Dubois E, Kasper E, Karmous A, Reckinger N, Flandre D, Francis LA, Colinge JP, Raskin JP. Energy-band engineering for improved charge retention in fully self-aligned double floating-gate single-electron memories. Nano Letters. 11: 4520-6. PMID 21967002 DOI: 10.1021/Nl202434K |
0.392 |
|
| 2011 |
Razavi P, Akhavan ND, Yu R, Fagas G, Ferain I, Colinge JP. Investigation of Short-Channel Effects in Junctionless Nanowire Transistors The Japan Society of Applied Physics. DOI: 10.7567/Ssdm.2011.P-3-12 |
0.409 |
|
| 2011 |
Colinge JP, Ferain I, Kranti A, Lee CW, Akhavan ND, Razavi P, Yan R, Yu R. Junctionless nanowire transistor: Complementary metal-oxide-semiconductor without junctions Science of Advanced Materials. 3: 477-482. DOI: 10.1166/Sam.2011.1163 |
0.536 |
|
| 2011 |
Doria RT, Pavanello MA, Trevisoli RD, Souza M, Lee CW, Ferain I, Dehdashti Akhavan N, Yan R, Razavi P, Yu R, Kranti A, Colinge JP. The roles of the electric field and the density of carriers in the improved output conductance of junctionless nanowire transistors Ecs Transactions. 35: 283-288. DOI: 10.1149/1.3570807 |
0.338 |
|
| 2011 |
Nazarov AN, Lee CW, Kranti A, Ferain I, Yan R, Dehdashti Akhavan N, Razavi P, Yu R, Colinge JP. Comparative study of random telegraph noise in junctionless and inversion-mode MuGFETs Ecs Transactions. 35: 73-78. DOI: 10.1149/1.3570779 |
0.361 |
|
| 2011 |
Colinge JP, Kranti A, Yan R, Ferain I, Dehdashti Akhavan N, Razavi P, Lee CW, Yu R, Colinge CA. A simulation comparison between junctionless and inversion-mode MuGFETs Ecs Transactions. 35: 63-72. DOI: 10.1149/1.3570778 |
0.429 |
|
| 2011 |
Razavi P, Fagas G, Ferain I, Akhavan ND, Yu R, Colinge JP. Performance investigation of short-channel junctionless multigate transistors 2011 12th International Conference On Ultimate Integration On Silicon, Ulis 2011. 122-125. DOI: 10.1109/ULIS.2011.5758005 |
0.388 |
|
| 2011 |
Nazarov AN, Lee CW, Kranti A, Ferain I, Yan R, Akhavan ND, Razavi P, Yu R, Colinge JP. Extraction of channel mobility in nanowire MOSFETs using Id(Vg) characteristics and random telegraph noise amplitude 2011 12th International Conference On Ultimate Integration On Silicon, Ulis 2011. 107-109. DOI: 10.1109/ULIS.2011.5757991 |
0.337 |
|
| 2011 |
Afzalian A, Lee CW, Dehdashti Akhavan N, Yan R, Ferain I, Colinge JP. Quantum confinement effects in capacitance behavior of multigate silicon nanowire MOSFETs Ieee Transactions On Nanotechnology. 10: 300-309. DOI: 10.1109/Tnano.2009.2039800 |
0.466 |
|
| 2011 |
Doria RT, Pavanello MA, Trevisoli RD, De Souza M, Lee CW, Ferain I, Akhavan ND, Yan R, Razavi P, Yu R, Kranti A, Colinge JP. Junctionless multiple-gate transistors for analog applications Ieee Transactions On Electron Devices. 58: 2511-2519. DOI: 10.1109/Ted.2011.2157826 |
0.541 |
|
| 2011 |
Akhavan ND, Afzalian A, Kranti A, Ferain I, Lee CW, Yan R, Razavi P, Yu R, Colinge JP. Influence of elastic and inelastic electronphonon interaction on quantum transport in multigate silicon nanowire MOSFETs Ieee Transactions On Electron Devices. 58: 1029-1037. DOI: 10.1109/Ted.2011.2107521 |
0.393 |
|
| 2011 |
Akhavan ND, Afzalian A, Lee CW, Yan R, Ferain I, Razavi P, Yu R, Fagas G, Colinge JP. Nanowire to single-electron transistor transition in trigate SOI MOSFETs Ieee Transactions On Electron Devices. 58: 26-32. DOI: 10.1109/Ted.2010.2084390 |
0.412 |
|
| 2011 |
De Souza M, Pavanello MA, Trevisoli RD, Doria RT, Colinge JP. Cryogenic operation of junctionless nanowire transistors Ieee Electron Device Letters. 32: 1322-1324. DOI: 10.1109/Led.2011.2161748 |
0.468 |
|
| 2011 |
Nazarov AN, Ferain I, Dehdashti Akhavan N, Razavi P, Yu R, Colinge JP. Field-effect mobility extraction in nanowire field-effect transistors by combination of transfer characteristics and random telegraph noise measurements Applied Physics Letters. 99. DOI: 10.1063/1.3626038 |
0.425 |
|
| 2011 |
Yu R, Ferain I, Akhavan ND, Razavi P, Duffy R, Colinge JP. Characterization of a junctionless diode Applied Physics Letters. 99. DOI: 10.1063/1.3608150 |
0.529 |
|
| 2011 |
Jang D, Lee JW, Lee CW, Colinge JP, Mont̀s L, Lee JI, Kim GT, Ghibaudo G. Low-frequency noise in junctionless multigate transistors Applied Physics Letters. 98. DOI: 10.1063/1.3569724 |
0.414 |
|
| 2011 |
Dehdashti Akhavan N, Ferain I, Razavi P, Yu R, Colinge JP. Improvement of carrier ballisticity in junctionless nanowire transistors Applied Physics Letters. 98. DOI: 10.1063/1.3559625 |
0.46 |
|
| 2011 |
Nazarov AN, Ferain I, Akhavan ND, Razavi P, Yu R, Colinge JP. Random telegraph-signal noise in junctionless transistors Applied Physics Letters. 98. DOI: 10.1063/1.3557505 |
0.452 |
|
| 2011 |
Colinge JP, Kranti A, Yan R, Lee CW, Ferain I, Yu R, Akhavan ND, Razavi P. Junctionless Nanowire Transistor (JNT): Properties and design guidelines Solid-State Electronics. 65: 33-37. DOI: 10.1016/j.sse.2011.06.004 |
0.484 |
|
| 2011 |
Afzalian A, Colinge JP, Flandre D. Physics of Gate Modulated Resonant Tunneling (RT)-FETs: Multi-barrier MOSFET for steep slope and high on-current Solid-State Electronics. 59: 50-61. DOI: 10.1016/J.Sse.2011.01.016 |
0.455 |
|
| 2011 |
Yan R, Kranti A, Ferain I, Lee C, Yu R, Dehdashti N, Razavi P, Colinge J. Investigation of high-performance sub-50 nm junctionless nanowire transistors Microelectronics Reliability. 51: 1166-1171. DOI: 10.1016/J.Microrel.2011.02.016 |
0.509 |
|
| 2011 |
Doria RT, Pavanello MA, Trevisoli RD, de Souza M, Lee CW, Ferain I, Akhavan ND, Yan R, Razavi P, Yu R, Kranti A, Colinge JP. Analog operation temperature dependence of nMOS junctionless transistors focusing on harmonic distortion Journal of Integrated Circuits and Systems. 6: 114-121. |
0.401 |
|
| 2010 |
Colinge JP, Lee CW, Afzalian A, Akhavan ND, Yan R, Ferain I, Razavi P, O'Neill B, Blake A, White M, Kelleher AM, McCarthy B, Murphy R. Nanowire transistors without junctions. Nature Nanotechnology. 5: 225-9. PMID 20173755 DOI: 10.1038/Nnano.2010.15 |
0.503 |
|
| 2010 |
Lee CW, Ferain I, Kranti A, Akhavan ND, Razavi P, Yan R, Yu R, O'Neill B, Blake A, White M, Kelleher AM, McCarthy B, Gheorghe S, Murphy R, Colinge JP. Short-Channel Junctionless Nanowire Transistors The Japan Society of Applied Physics. DOI: 10.7567/Ssdm.2010.C-9-5L |
0.399 |
|
| 2010 |
Colinge JP, Raskin JP, Kranti A, Ferain I, Lee CW, Akhavan ND, Razavi P, Yan R, Yu R. Analysis of the Junctionless Transistor Architecture The Japan Society of Applied Physics. DOI: 10.7567/Ssdm.2010.C-9-4 |
0.325 |
|
| 2010 |
Doria RT, Pavanello MA, Lee CW, Ferain I, Dehdashti-Akhavan N, Yan R, Razavi P, Yu R, Kranti A, Colinge JP. Analog operation and harmonic distortion temperature dependence of nMOS junctionless transistors Ecs Transactions. 31: 13-20. DOI: 10.1149/1.3474137 |
0.411 |
|
| 2010 |
Yan R, Duane R, Razavi P, Afzalian A, Ferain I, Lee CW, Dehdashti N, Nguyen BY, Bourdelle KK, Colinge JP. Back-gate mirror doping for fully depleted planar SOI transistors with thin buried oxide Proceedings of 2010 International Symposium On Vlsi Technology, System and Application, Vlsi-Tsa 2010. 76-77. DOI: 10.1109/VTSA.2010.5488939 |
0.409 |
|
| 2010 |
Yan R, Duane R, Razavi P, Afzalian A, Ferain I, Lee CW, Akhavan ND, Nguyen BY, Bourdelle KK, Colinge JP. LDD and back-gate engineering for fully depleted planar SOI transistors with thin buried oxide Ieee Transactions On Electron Devices. 57: 1319-1326. DOI: 10.1109/Ted.2010.2046097 |
0.503 |
|
| 2010 |
Akhavan ND, Afzalian A, Lee CW, Yan R, Ferain I, Razavi P, Fagas G, Colinge JP. Simulation of quantum current oscillations in trigate SOI MOSFETs Ieee Transactions On Electron Devices. 57: 1102-1109. DOI: 10.1109/Ted.2010.2044295 |
0.412 |
|
| 2010 |
Lee CW, Borne A, Ferain I, Afzalian A, Yan R, Dehdashti Akhavan N, Razavi P, Colinge JP. High-temperature performance of silicon junctionless MOSFETs Ieee Transactions On Electron Devices. 57: 620-625. DOI: 10.1109/TED.2009.2039093 |
0.414 |
|
| 2010 |
Dehdashti N, Kranti A, Ferain I, Lee CW, Yan R, Razavi P, Yu R, Colinge JP. Dissipative transport in multigate silicon nanowire transistors International Conference On Simulation of Semiconductor Processes and Devices, Sispad. 97-100. DOI: 10.1109/SISPAD.2010.5604559 |
0.406 |
|
| 2010 |
Lee CW, Yan R, Ferain I, Kranti A, Akhavan ND, Razavi P, Yu R, Colinge JP. Nanowire zero-capacitor DRAM transistors with and without junctions 2010 10th Ieee Conference On Nanotechnology, Nano 2010. 242-245. DOI: 10.1109/NANO.2010.5697888 |
0.323 |
|
| 2010 |
Park JT, Kim JY, Lee CW, Colinge JP. Low-temperature conductance oscillations in junctionless nanowire transistors Applied Physics Letters. 97. DOI: 10.1063/1.3506899 |
0.533 |
|
| 2010 |
Ansari L, Feldman B, Fagas G, Colinge JP, Greer JC. Simulation of junctionless Si nanowire transistors with 3 nm gate length Applied Physics Letters. 97. DOI: 10.1063/1.3478012 |
0.449 |
|
| 2010 |
Raskin JP, Colinge JP, Ferain I, Kranti A, Lee CW, Dehdashti N, Yan R, Razavi P, Yu R. Mobility improvement in nanowire junctionless transistors by uniaxial strain Proceedings - Ieee International Soi Conference. DOI: 10.1063/1.3474608 |
0.372 |
|
| 2010 |
Akhavan ND, Afzalian A, Lee CW, Yan R, Ferain I, Razavi P, Yu R, Fagas G, Colinge JP. Effect of intravalley acoustic phonon scattering on quantum transport in multigate silicon nanowire metal-oxide-semiconductor field-effect transistors Journal of Applied Physics. 108. DOI: 10.1063/1.3457848 |
0.441 |
|
| 2010 |
Lee CW, Nazarov AN, Ferain I, Akhavan ND, Yan R, Razavi P, Yu R, Doria RT, Colinge JP. Low subthreshold slope in junctionless multigate transistors Applied Physics Letters. 96. DOI: 10.1063/1.3358131 |
0.498 |
|
| 2010 |
Colinge JP, Lee CW, Ferain I, Akhavan ND, Yan R, Razavi P, Yu R, Nazarov AN, Doria RT. Reduced electric field in junctionless transistors Applied Physics Letters. 96. DOI: 10.1063/1.3299014 |
0.398 |
|
| 2010 |
Barrett C, Lederer D, Redmond G, Xiong W, Colinge JP, Quinn AJ. Variable temperature characterization of low-dimensional effects in tri-gate SOI MOSFETs Solid-State Electronics. 54: 1273-1277. DOI: 10.1016/J.Sse.2010.05.035 |
0.695 |
|
| 2010 |
Lee CW, Ferain I, Afzalian A, Yan R, Akhavan ND, Razavi P, Colinge JP. Performance estimation of junctionless multigate transistors Solid-State Electronics. 54: 97-103. DOI: 10.1016/J.Sse.2009.12.003 |
0.488 |
|
| 2010 |
Lee CW, Afzalian A, Ferain I, Yan R, Akhavan ND, Xiong W, Colinge JP. Influence of gate misalignment on the electrical characteristics of MuGFETS Solid-State Electronics. 54: 226-230. DOI: 10.1016/J.Sse.2009.09.001 |
0.701 |
|
| 2009 |
Afzalian A, Lee CW, Yan R, Akhavan ND, Colinge C, Colinge JP. Quantization effect in capacitance behavior of nanoscale silicon multigate MOSFETs Ecs Transactions. 19: 321-327. DOI: 10.1149/1.3117425 |
0.345 |
|
| 2009 |
Colinge JP, Lederer D, Afzalian A, Yan R, Lee CW, Akhavan ND, Xiong W. Properties of accumulation-mode multi-gate field-effect transistors Japanese Journal of Applied Physics. 48: 034502. DOI: 10.1143/Jjap.48.034502 |
0.738 |
|
| 2009 |
Yan R, Duane R, Razavi P, Afzalian A, Ferain I, Lee CW, Dehdashti-Akhavan N, Bourdelle K, Nguyen BY, Colinge JP. LDD depletion effects in thin-BOX FDSOI devices with a ground plane Proceedings - Ieee International Soi Conference. DOI: 10.1109/SOI.2009.5318771 |
0.412 |
|
| 2009 |
Colinge JP, Lee CW, Afzalian A, Dehdashti N, Yan R, Ferain I, Razavi P, O'Neill B, Blake A, White M, Kelleher AM, McCarthy B, Murphy R. SOI gated resistor: CMOS without junctions Proceedings - Ieee International Soi Conference. DOI: 10.1109/SOI.2009.5318737 |
0.377 |
|
| 2009 |
Dehdashti N, Afzalian A, Lee CW, Yan R, Fagas G, Colinge JP. Device characteristics of Trigate-FET with barrier constrictions in the channel Proceedings - 2009 13th International Workshop On Computational Electronics, Iwce 2009. DOI: 10.1109/IWCE.2009.5091103 |
0.463 |
|
| 2009 |
Lee CW, Ferain I, Afzalian A, Byun KY, Yan R, Dehdashti N, Razavi P, Xiong W, Colinge JP, Colinge CA, Ioannou DE. Hot carrier (HC) and Bias-Temperature-Instability (BTI) degradation of MuGFETs on silicon oxide and silicon nitride buried layers Essderc 2009 - Proceedings of the 39th European Solid-State Device Research Conference. 261-264. DOI: 10.1109/ESSDERC.2009.5331453 |
0.369 |
|
| 2009 |
Lee CW, Afzalian A, Akhavan ND, Yan R, Ferain I, Colinge JP. Junctionless multigate field-effect transistor Applied Physics Letters. 94. DOI: 10.1063/1.3079411 |
0.525 |
|
| 2009 |
Lee CW, Ferain I, Afzalian A, Yan R, Dehdashti N, Razavi P, Colinge JP, Park JT. NBTI and hot-carrier effects in accumulation-mode Pi-gate pMOSFETs Microelectronics Reliability. 49: 1044-1047. DOI: 10.1016/J.Microrel.2009.06.011 |
0.507 |
|
| 2009 |
Lee CW, Afzalian A, Ferain I, Yan R, Dehdashti N, Byun KY, Colinge C, Xiong W, Colinge JP. Comparison of different surface orientation in narrow fin MuGFETs Microelectronic Engineering. 86: 2381-2384. DOI: 10.1016/J.Mee.2009.04.025 |
0.684 |
|
| 2009 |
Lee CW, Lederer D, Afzalian A, Yan R, Akhavan ND, Colinge JP. Analytical model for the high-temperature behaviour of the subthreshold slope in MuGFETs Microelectronic Engineering. 86: 2067-2071. DOI: 10.1016/J.Mee.2009.01.061 |
0.409 |
|
| 2009 |
Afzalian A, Akhavan ND, Lee CW, Yan R, Ferain I, Razavi P, Colinge JP. A new F(ast)-CMS NEGF algorithm for efficient 3D simulations of switching characteristics enhancement in constricted tunnel barrier silicon nanowire MuGFETs Journal of Computational Electronics. 8: 287-306. DOI: 10.1007/S10825-009-0283-1 |
0.417 |
|
| 2008 |
Lee CW, Afzalian A, Yan R, Akhavan ND, Xiong W, Colinge JP. Drain breakdown voltage in MuGFETs: Influence of physical parameters Ieee Transactions On Electron Devices. 55: 3503-3506. DOI: 10.1109/Ted.2008.2006546 |
0.636 |
|
| 2008 |
Lee CW, Afzalian A, Yan R, Dehdashti N, Xiong W, Colinge JP. Influence of gate underlap in AM and im MuGFETs Essderc 2008 - Proceedings of the 38th European Solid-State Device Research Conference. 238-241. DOI: 10.1109/ESSDERC.2008.4681742 |
0.412 |
|
| 2008 |
Colinge JP, Afzalian A, Lee CW, Yan R, Akhavan ND. Influence of carrier confinement on the subthreshold swing of multigate silicon-on-insulator transistors Applied Physics Letters. 92. DOI: 10.1063/1.2907330 |
0.527 |
|
| 2008 |
Yan R, Afzalian A, Lee CW, Akhavan DN, Xiong W, Colinge JP. Accumulation-mode and inversion-mode triple-gate MOSFETs Iet Conference Publications. 627-630. DOI: 10.1049/cp:20080883 |
0.439 |
|
| 2008 |
Lee CW, Lederer D, Afzalian A, Yan R, Dehdashti N, Xiong W, Colinge JP. Comparison of contact resistance between accumulation-mode and inversion-mode multigate FETs Solid-State Electronics. 52: 1815-1820. DOI: 10.1016/J.Sse.2008.09.006 |
0.634 |
|
| 2008 |
Yan R, Lynch D, Cayron T, Lederer D, Afzalian A, Lee CW, Dehdashti N, Colinge JP. Sensitivity of trigate MOSFETs to random dopant induced threshold voltage fluctuations Solid-State Electronics. 52: 1872-1876. DOI: 10.1016/J.Sse.2008.06.061 |
0.508 |
|
| 2008 |
Yun SRN, Yu CG, Park JT, Colinge JP. Quantum-mechanical effects in nanometer scale MuGFETs Microelectronic Engineering. 85: 1717-1722. DOI: 10.1016/J.Mee.2008.04.023 |
0.495 |
|
| 2008 |
Colinge JP. The new generation of soi mosfets Romanian Journal of Information Science and Technology. 11: 3-15. |
0.441 |
|
| 2007 |
Yun SRN, Yu CG, Park JT, Lee CW, Lederer D, Afzalian A, Yan R, Colinge JP. A quantum definition of threshold voltage in MuGFETs Proceedings - Ieee International Soi Conference. 137-138. DOI: 10.1109/SOI.2007.4357890 |
0.34 |
|
| 2007 |
Patruno P, Kostrzewa M, Landry K, Xiong W, Rinn Cleavelin C, Hsu CH, Ma M, Colinge JP. Study of fin profiles and MuGFETs built on SOI wafers with a Nitride-Oxide Buried Layer (NOx-BL) as the buried insulator layer Proceedings - Ieee International Soi Conference. 51-52. DOI: 10.1109/SOI.2007.4357847 |
0.339 |
|
| 2007 |
Colinge JP. From gate-all-around to nanowire MOSFETs Proceedings of the International Semiconductor Conference, Cas. 1: 11-17. DOI: 10.1109/SMICND.2007.4519637 |
0.379 |
|
| 2007 |
Colinge JP. Quantum-wire effects in trigate SOI MOSFETs Solid-State Electronics. 51: 1153-1160. DOI: 10.1016/J.Sse.2007.07.019 |
0.472 |
|
| 2007 |
Lee CW, Yun SRN, Yu CG, Park JT, Colinge JP. Device design guidelines for nano-scale MuGFETs Solid-State Electronics. 51: 505-510. DOI: 10.1016/J.Sse.2006.11.013 |
0.514 |
|
| 2007 |
Colinge JP. Multi-gate SOI MOSFETs Microelectronic Engineering. 84: 2071-2076. DOI: 10.1016/J.Mee.2007.04.038 |
0.523 |
|
| 2007 |
Colinge JP. Nanowire quantum effects in trigate SOI MOSFETs Nato Security Through Science Series C: Environmental Security. 129-142. DOI: 10.1007/978-1-4020-6380-0_9 |
0.355 |
|
| 2007 |
Xiong W, Cleavelin CR, Schulz T, Schrüfer K, Patruno P, Colinge JP. MuGFET CMOS process with midgap gate material Nato Security Through Science Series C: Environmental Security. 159-164. DOI: 10.1007/978-1-4020-6380-0_11 |
0.406 |
|
| 2006 |
Colinge JP, Orozco A, Rudee J, Xiong W, Cleavelin CR, Schulz T, Schrüfer K, Knoblinger G, Patruno P. Radiation dose effects in trigate SOI MOS transistors Ieee Transactions On Nuclear Science. 53: 3237-3241. DOI: 10.1109/Tns.2006.885841 |
0.648 |
|
| 2006 |
Colinge JP, Alderman JC, Xiong W, Cleavelin CR. Quantum - Mechanical effects in trigate SOI MOSFETs Ieee Transactions On Electron Devices. 53: 1131-1136. DOI: 10.1109/Ted.2006.871872 |
0.658 |
|
| 2006 |
Colinge JP, Xiong W, Cleavelin CR, Schulz T, Schrüfer K, Matthews K, Patruno P. Room-temperature low-dimensional effects in Pi-Gate SOI MOSFETs Ieee Electron Device Letters. 27: 775-777. DOI: 10.1109/Led.2006.881086 |
0.664 |
|
| 2006 |
Colinge JP, Floyd L, Quinn AJ, Redmond G, Alderman JC, Xiong W, Cleavelin CR, Schulz T, Schruefer K, Knoblinger G, Patruno P. Temperature effects on trigate SOI MOSFETs Ieee Electron Device Letters. 27: 172-174. DOI: 10.1109/Led.2006.869941 |
0.64 |
|
| 2006 |
Colinge JP, Quinn AJ, Floyd L, Redmond G, Alderman JC, Xiong W, Cleavelin CR, Schulz T, Schruefer K, Knoblinger G, Patruno P. Low-temperature electron mobility in trigate SOI MOSFETs Ieee Electron Device Letters. 27: 120-122. DOI: 10.1109/Led.2005.862691 |
0.611 |
|
| 2006 |
Wu X, Chan PCH, Orozco A, Vazquez A, Chaudhry A, Colinge JP. Dose radiation effects in FinFETs Solid-State Electronics. 50: 287-290. DOI: 10.1016/J.Sse.2005.12.017 |
0.411 |
|
| 2005 |
Schulz T, Xiong W, Cleavelin CR, Schruefer K, Gostkowski M, Matthews K, Gebara G, Zaman RJ, Patruno P, Chaudhry A, Woo A, Colinge JP. Fin thickness asymmetry effects in multiple-gate SOI FETs (MuGFETs) Proceedings - Ieee International Soi Conference. 2005: 154-156. DOI: 10.1109/SOI.2005.1563571 |
0.419 |
|
| 2005 |
Xiong W, Rinn Cleavelin C, Wise R, Yu S, Pas M, Zaman RJ, Gostkowski M, Matthews K, Maleville C, Patruno P, King TJ, Colinge JP. Full/partial depletion effects in FinFETs Electronics Letters. 41: 504-506. DOI: 10.1049/El:20050281 |
0.699 |
|
| 2004 |
Pinardi K, Heinle U, Bengtsson S, Olsson J, Colinge JP. High-power SOI vertical DMOS transistors with lateral drain contacts: Process developments, characterization, and modeling Ieee Transactions On Electron Devices. 51: 790-796. DOI: 10.1109/TED.2004.825801 |
0.389 |
|
| 2004 |
Frei J, Johns C, Vazquez A, Xiong W, Cleavelin CR, Schulz T, Chaudhary N, Gebara G, Zaman JR, Gostkowski M, Matthews K, Colinge JP. Body effect in tri- and pi-gate SOI MOSFETs Ieee Electron Device Letters. 25: 813-815. DOI: 10.1109/Led.2004.839223 |
0.684 |
|
| 2004 |
Xiong W, Gebara G, Zaman J, Gostkowski M, Nguyen B, Smith G, Lewis D, Cleavelin CR, Wise R, Yu S, Pas M, King TJ, Colinge JP. Improvement of FinFET electrical characteristics by hydrogen annealing Ieee Electron Device Letters. 25: 541-543. DOI: 10.1109/Led.2004.832787 |
0.646 |
|
| 2004 |
Lee JK, Choi NJ, Yu CG, Colinge JP, Park JT. Temperature dependence of DTMOS transistor characteristics Solid-State Electronics. 48: 183-187. DOI: 10.1016/S0038-1101(03)00297-1 |
0.447 |
|
| 2004 |
Pinardi K, Heinle U, Bengtsson S, Olsson J, Colinge JP. Electrothermal simulations of high-power SOI vertical DMOS transistors with lateral drain contacts under unclamped inductive switching test Solid-State Electronics. 48: 1119-1126. DOI: 10.1016/J.Sse.2004.02.010 |
0.507 |
|
| 2004 |
Colinge JP. Multiple-gate SOI MOSFETs Solid-State Electronics. 48: 897-905. DOI: 10.1016/J.Sse.2003.12.020 |
0.544 |
|
| 2004 |
Rudenko T, Rudenko A, Kilchytska V, Cristoloveanu S, Ernst T, Colinge JP, Dessard V, Flandre D. Determination of film and surface recombination in thin-film SOI devices using gated-diode technique Solid-State Electronics. 48: 389-399. DOI: 10.1016/j.sse.2003.09.004 |
0.33 |
|
| 2004 |
Yun SRN, Yu CG, Jeon SH, Kim CK, Park JT, Colinge JP. Reduced hot carrier effects in self-aligned ground-plane FDSOI MOSFET's Microelectronics Reliability. 44: 1649-1654. DOI: 10.1016/j.microrel.2004.07.085 |
0.379 |
|
| 2004 |
Colinge JP. Novel gate concepts for MOS devices Esscirc 2004 - Proceedings of the 34th European Solid-State Device Research Conference. 45-50. |
0.392 |
|
| 2004 |
Colinge JP. SOI for hostile environment applications Proceedings - Ieee International Soi Conference. 1-4. |
0.401 |
|
| 2003 |
Colinge JP. Evolution of SOI MOSFETs: From single gate to multiple gates Materials Research Society Symposium - Proceedings. 765: 9-20. DOI: 10.1557/Proc-765-D1.6 |
0.54 |
|
| 2003 |
Colinge JP, Park JW, Xiong W. Threshold voltage and subthreshold slope of multiple-gate SOI MOSFETs Ieee Electron Device Letters. 24: 515-517. DOI: 10.1109/Led.2003.815153 |
0.554 |
|
| 2003 |
Park JT, Choi NJ, Yu CG, Jeon SH, Colinge JP. Increased hot carrier effects in Gate-All-Around SOI nMOSFET's Microelectronics Reliability. 43: 1427-1432. DOI: 10.1016/S0026-2714(03)00254-3 |
0.492 |
|
| 2003 |
Park JW, Xiong W, Colinge JP. Accumulation-Mode Pi-gate MOSFET Ieee International Soi Conference. 65-67. |
0.321 |
|
| 2003 |
Xiong W, Park JW, Colinge JP. Corner Effect in Multiple-Gate SOI MOSFETs Ieee International Soi Conference. 111-113. |
0.497 |
|
| 2002 |
Park JT, Colinge JP. Multiple-gate SOI MOSFETs: Device design guidelines Ieee Transactions On Electron Devices. 49: 2222-2229. DOI: 10.1109/TED.2002.805634 |
0.35 |
|
| 2002 |
Tang X, Baie X, Colinge JP, Gustin C, Bayot V. Two-dimensional self-consistent simulation of a triangular P-channel SOI nano-flash memory device Ieee Transactions On Electron Devices. 49: 1420-1426. DOI: 10.1109/TED.2002.801307 |
0.435 |
|
| 2002 |
Colinge JP, Park JT, Colinge CA. SOI devices for sub-0.1 μm gate lengths 2002 23rd International Conference On Microelectronics, Miel 2002 - Proceedings. 1: 109-113. DOI: 10.1109/MIEL.2002.1003156 |
0.435 |
|
| 2002 |
Lee JK, Choi NJ, Yu CG, Colinge JP, Park JT. Temperature dependence of hot-carrier degradation in silicon-on-insulator dynamic threshold voltage MOS transistors Ieee Electron Device Letters. 23: 673-675. DOI: 10.1109/LED.2002.805009 |
0.413 |
|
| 2002 |
Lee JK, Choi NJ, Hyun YB, Yu CG, Colinge JP, Park JT. Hot carrier-induced SOI MOSFET degradation under ac stress conditions Ieee Electron Device Letters. 23: 157-159. DOI: 10.1109/55.988823 |
0.463 |
|
| 2002 |
Rudenko T, Kilchytska V, Colinge JP, Dessard V, Flandre D. On the high-temperature subthreshold slope of thin-film SOI MOSFETs Ieee Electron Device Letters. 23: 148-150. DOI: 10.1109/55.988820 |
0.382 |
|
| 2002 |
Pinardi K, Heinle U, Bengtsson S, Olsson J, Colinge JP. Unclamped inductive switching behaviour of high power SOI vertical DMOS transistors with lateral drain contacts Solid-State Electronics. 46: 2105-2110. DOI: 10.1016/S0038-1101(02)00227-7 |
0.503 |
|
| 2001 |
Colinge J, Park J. Future SOI Technology and Devices The Japan Society of Applied Physics. 2001: 238-239. DOI: 10.7567/Ssdm.2001.C-3-1 |
0.404 |
|
| 2001 |
Park JT, Colinge JP, Diaz CH. Pi-gate SOI MOSFET Ieee Electron Device Letters. 22: 405-406. DOI: 10.1109/55.936358 |
0.361 |
|
| 2001 |
Vandooren A, Yuan J, Flandre D, Colinge JP. Total-dose effects in double-gate-controlled NPN bipolar transistors Ieee Transactions On Nuclear Science. 48: 1694-1699. DOI: 10.1109/23.960359 |
0.457 |
|
| 2001 |
Vandooren A, Cristoloveanu S, Flandre D, Colinge JP. Hall effect measurements in double-gate SOI MOSFETs Solid-State Electronics. 45: 1793-1798. DOI: 10.1016/S0038-1101(01)00207-6 |
0.432 |
|
| 2001 |
Tang X, Baie X, Colinge JP, Loumaye P, Renaux C, Bayot V. Influence of device geometry on SOI single-hole transistor characteristics Microelectronics Reliability. 41: 1841-1846. DOI: 10.1016/S0026-2714(01)00044-0 |
0.496 |
|
| 2000 |
Tang X, Baie X, Colinge JP, Van De Wiele F, Bayot V. Quantum effects in SOI single-hole transistors European Solid-State Device Research Conference. 220-223. DOI: 10.1109/ESSDERC.2000.194754 |
0.304 |
|
| 2000 |
Tang X, Baie X, Colinge JP, Crahay A, Katschmarsyj B, Scheuren V, Spôte D, Reckinger N, Van De Wiele F, Bayot V. Self-aligned silicon-on-insulator nano flash memory device Solid-State Electronics. 44: 2259-2264. DOI: 10.1016/S0038-1101(00)00221-5 |
0.561 |
|
| 2000 |
Vandooren A, Cristoloveanu S, Colinge JP. Hall mobility measurement in Double-Gate SOI MOSFETs Ieee International Soi Conference. 118-119. |
0.483 |
|
| 2000 |
Vandooren A, Cristoloveanu S, Colinge JP. Dynamic conductance and transconductance in Double-Gate (Gate-All-Around) SOI devices Ieee International Soi Conference. 116-117. |
0.438 |
|
| 1999 |
Ernst T, Vandooren A, Cristoloveanu S, Colinge JP, Flandre D. Carrier lifetime extraction in fully depleted dual-gate SOI devices Ieee Electron Device Letters. 20: 209-211. DOI: 10.1109/55.761017 |
0.37 |
|
| 1999 |
Vandooren A, Colinge JP, Flandre D. Gate-all-around ota's for rad-hard and high-temperature analog applications Ieee Transactions On Nuclear Science. 46: 1242-1249. DOI: 10.1109/23.785739 |
0.373 |
|
| 1999 |
Ernst T, Cristoloveanu S, Vandooren A, Rudenko T, Colinge JP. Recombination current modeling and carrier lifetime extraction in dual-gate fully-depleted SOI devices Ieee Transactions On Electron Devices. 46: 1503-1509. DOI: 10.1109/16.772502 |
0.396 |
|
| 1999 |
Xiong W, Colinge JP. Self-aligned implanted ground-plane fully depleted SOI MOSFET Electronics Letters. 35: 2059-2060. DOI: 10.1049/El:19991390 |
0.673 |
|
| 1999 |
Flandre D, Colinge JP, Chen J, De Ceuster D, Eggermont JP, Ferreira L, Gentinne B, Jespers PGA, Viviani A, Gillon R, Raskin JP, Vander Vorst A, Vanhoenacker-Janvier D, Silveira F. Fully-depleted SOI CMOS technology for low-voltage low-power mixed digital/analog/microwave circuits Analog Integrated Circuits and Signal Processing. 21: 213-228. DOI: 10.1023/A:1008321919587 |
0.414 |
|
| 1999 |
Nazarov AN, Barchuk IP, Lysenko VS, Colinge JP. Association of high-temperature kink-effect in SIMOX SOI fully depleted n-MOSFET with bias temperature instability of buried oxide Microelectronic Engineering. 48: 379-382. DOI: 10.1016/S0167-9317(99)00410-4 |
0.323 |
|
| 1999 |
Tang X, Baie X, Bayot V, Van de Wiele F, Colinge JP. SOI single-electron transistor Ieee International Soi Conference. 46-47. |
0.359 |
|
| 1999 |
Tang X, Baie X, Bayot V, Van de Wiele F, Colinge JP. SOI nano flash memory device Ieee International Soi Conference. 100-101. |
0.343 |
|
| 1998 |
Colinge JP. Silicon-on-insulator technology: Past achievements and future prospects Mrs Bulletin. 23: 16-19. DOI: 10.1557/S0883769400029778 |
0.306 |
|
| 1998 |
Lysenko VS, Nazarov A, Kilchytska V, Rudenko T, Limanov AB, Colinge J. High-temperature characteristics of zone-melting recrystallized silicon-on-insulator MOSFETs Semiconductor Physics, Quantum Electronics and Optoelectronics. 1: 101-107. DOI: 10.15407/Spqeo1.01.101 |
0.528 |
|
| 1998 |
Tang X, Baie X, Colinge JP. Fabrication of twin nano silicon wires based on arsenic dopant effect Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 37: 1591-1593. DOI: 10.1143/Jjap.37.1591 |
0.436 |
|
| 1998 |
Colinge JP. Fully-depleted SOI CMOS for analog applications Ieee Transactions On Electron Devices. 45: 1010-1016. DOI: 10.1109/16.669511 |
0.374 |
|
| 1998 |
Baie X, Colinge JP. Two-dimensional confinement effects in gate-all-around (GAA) MOSFETs Solid-State Electronics. 42: 499-504. DOI: 10.1016/S0038-1101(98)00061-6 |
0.432 |
|
| 1998 |
Vandooren A, Flandre D, Cristoloveanu S, Colinge JP. Edge effects characterization in gate-all-around SOI MOSFETs Ieee International Soi Conference. 75-76. |
0.402 |
|
| 1998 |
Ernst T, Cristoloveanu S, Vandooren A, Colinge JP, Rudenko TE. Carrier lifetime extraction in fully-depleted SOI devices Ieee International Soi Conference. 21-22. |
0.362 |
|
| 1998 |
Ernst T, Cristoloveanu S, Vandooren A, Colinge JP, Flandre D. Recombination current and carrier lifetime extraction in dual-gate fully depleted SOI devices European Solid-State Device Research Conference. 272-275. |
0.406 |
|
| 1997 |
Tang X, Baie X, Colinge JP. Fabrication Process of Si Memory Dot and Quantum Channel Based on As Dopant Statistical Distribution Effect The Japan Society of Applied Physics. 1997: 484-485. DOI: 10.7567/Ssdm.1997.B-13-5 |
0.336 |
|
| 1997 |
Bondarenko VP, Bogatirev YV, Colinge JP, Dolgyi LN, Dorofeev AM, Yakovtseva VA. Total gamma dose characteristics of CMOS devices in soi structures based on oxidized porous silicon Ieee Transactions On Nuclear Science. 44: 1719-1723. DOI: 10.1109/23.633424 |
0.521 |
|
| 1997 |
Gentinne B, Eggermont JP, Flandre D, Colinge JP. Fully depleted SOI-CMOS technology for high temperature IC applications Materials Science and Engineering B. 46: 1-7. DOI: 10.1016/S0921-5107(96)01921-6 |
0.351 |
|
| 1997 |
Pavanello MA, Martino JA, Colinge JP. Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77 K Microelectronic Engineering. 36: 375-378. DOI: 10.1016/S0167-9317(97)00083-X |
0.381 |
|
| 1997 |
Chen J, Colinge J. Study on titanium salicide process for thin-film SOI devices Microelectronic Engineering. 33: 189-194. DOI: 10.1016/S0167-9317(96)00044-5 |
0.436 |
|
| 1997 |
Pavanello MA, Martino JA, Colinge JP. Analytical modeling of the substrate influences on accumulation-mode SOI pMOSFETs at room temperature and at liquid nitrogen temperature Solid-State Electronics. 41: 1241-1247. DOI: 10.1016/S0038-1101(97)00071-3 |
0.432 |
|
| 1997 |
Pavanello MA, Martino JA, Colinge JP. Substrate influences on fully depleted enhancement mode SOI MOSFETs at room temperature and at 77 K Solid-State Electronics. 41: 111-119. DOI: 10.1016/S0038-1101(96)00126-8 |
0.414 |
|
| 1997 |
Vandooren A, Francis P, Flandre D, Colinge JP. Performance of γ-irradiated gate-all-around SOI MOS OTA amplifiers Ieee International Soi Conference. 62-63. |
0.36 |
|
| 1997 |
Francis P, Colinge JP, Flandre D. Comparison of self-heating effect in GAA and SOI MOSFETs Microelectronics Reliability. 37: 61-75. |
0.335 |
|
| 1996 |
Colinge JP, Crahay A, De Ceuster D, Dessard V, Gentinne B. Improved LOCOS isolation for thin-film SOI MOSFETs Electronics Letters. 32: 1834-1835. DOI: 10.1049/El:19961210 |
0.349 |
|
| 1996 |
De Ceuster D, Flandre D, Colinge JP, Cristoloveanu S. Improvement of SOI MOS current-mirror performances using serial-parallel association of transistors Electronics Letters. 32: 278-279. DOI: 10.1049/El:19960252 |
0.409 |
|
| 1996 |
Gentinne B, Flandre D, Colinge JP, Van De Wiele F. Measurement and two-dimensional simulation of thin-film SOI MOSFETs: Intrinsic gate capacitances at elevated temperatures Solid-State Electronics. 39: 1613-1619. DOI: 10.1016/0038-1101(96)00067-6 |
0.329 |
|
| 1996 |
Gentinne B, Flandre D, Colinge JP. Measurement and modeling of thin-film accumulation-mode SOI p-MOSFET intrinsic gate capacitances Solid-State Electronics. 39: 1071-1078. DOI: 10.1016/0038-1101(95)00408-4 |
0.467 |
|
| 1996 |
Flandre D, Ferreira LF, Jespers PGA, Colinge JP. Modelling and application of fully depleted SOI MOSFETs for low voltage, low power analogue CMOS circuits Solid-State Electronics. 39: 455-460. DOI: 10.1016/0038-1101(95)00167-0 |
0.456 |
|
| 1996 |
Colinge JP, Baie X, Bayot V, Grivei E. A silicon-on-insulator quantum wire Solid-State Electronics. 39: 49-51. |
0.402 |
|
| 1996 |
Colinge JP, Chen J, Flandre D, Raskin JP, Gillon R, Vanhoenacker D. Low-voltage, low-power microwave SOI MOSFET Ieee International Soi Conference. 128-129. |
0.314 |
|
| 1996 |
Colinge JP. Recent advances and trends in SOI CMOS technology European Solid-State Device Research Conference. 935-942. |
0.32 |
|
| 1995 |
Gentinne B, Eggermont JP, Colinge JP. Performances of Soi Cmos Ota Combining Ztc and Gain-boosting Techniques Electronics Letters. 31: 2092-2093. DOI: 10.1049/El:19951418 |
0.307 |
|
| 1995 |
Verhaege K, Groeseneken G, Colinge J, Maes HE. The ESD protection mechanisms and the related failure modes and mechanisms observed in SOI snapback nMOSFET's Microelectronics Reliability. 35: 555-566. DOI: 10.1016/0026-2714(95)93075-L |
0.369 |
|
| 1994 |
Francis P, Baie X, Colinge JP. Some Properties of SOI Gate-All-Around Devices The Japan Society of Applied Physics. DOI: 10.7567/Ssdm.1994.S-Ii-9 |
0.487 |
|
| 1994 |
Colinge JP, Baie X, Bayot V. Evidence of two-dimensional carrier confinement in thin n-channel SOI gate-all-around (GAA) devices Ieee Electron Device Letters. 15: 193-195. DOI: 10.1109/55.286689 |
0.547 |
|
| 1994 |
Francis P, Michel C, Flandre D, Colinge JP. Radiation-hard design for SOI MOS inverters Ieee Transactions On Nuclear Science. 41: 402-407. DOI: 10.1109/23.281534 |
0.32 |
|
| 1994 |
Colinge JP, Flandre D, Ceuster DD. P+-p-p+ Pseudo-bipolar Lateral Soi Transistor Electronics Letters. 30: 1543-1545. DOI: 10.1049/El:19941040 |
0.432 |
|
| 1994 |
Colinge JP, Flandre D, Wiele FVd. Subthreshold slope of long-channel accumulation-mode p-channel SOI MOSFETs Solid-State Electronics. 37: 289-294. DOI: 10.1016/0038-1101(94)90080-9 |
0.427 |
|
| 1993 |
Simoen E, Gao MH, Colinge JP, Claeys C. Metastable charge-trapping effect in SOI nMOSTs at 4.2 K Semiconductor Science and Technology. 8: 423-428. DOI: 10.1088/0268-1242/8/3/021 |
0.381 |
|
| 1993 |
Smeys P, Colinge JP. Analysis of drain breakdown voltage in enhancement-mode SOI MOSFETs Solid-State Electronics. 36: 569-573. DOI: 10.1016/0038-1101(93)90268-U |
0.545 |
|
| 1993 |
Smeys P, Magnusson U, Colinge JP. Nondestructive Characterization of Soi Wafers Using Spectroscopic Reflectometry Solid-State Electronics. 36: 1213-1216. DOI: 10.1016/0038-1101(93)90203-3 |
0.315 |
|
| 1992 |
Gao M, Colinge J, Lauwers L, Wu S, Clayes C. Twin-MOSFET structure for suppression of kink and parasitic bipolar effects in SOI MOSFETs at room and liquid helium temperatures Solid-State Electronics. 35: 505-512. DOI: 10.1016/0038-1101(92)90112-P |
0.508 |
|
| 1991 |
Colinge J. An overview of CMOS-SOI technology and its potential use in particle detection systems Nuclear Instruments & Methods in Physics Research Section a-Accelerators Spectrometers Detectors and Associated Equipment. 305: 615-619. DOI: 10.1016/0168-9002(91)90164-L |
0.393 |
|
| 1990 |
Martino JA, Lauwers L, Colinge JP, Meyer Kd. Model for the potential drop in the silicon substrate for thin-film SOI MOSFETs Electronics Letters. 26: 1462-1464. DOI: 10.1049/El:19900938 |
0.421 |
|
| 1989 |
Haond M, Colinge JP. Analysis of drain breakdown voltage in SOI n-channel MOSFETs Electronics Letters. 25: 1640-1641. DOI: 10.1049/El:19891099 |
0.488 |
|
| 1987 |
Colinge JP, Kamins TI. CMOS circuits made in thin SIMOX films Electronics Letters. 23: 1162-1164. DOI: 10.1049/El:19870810 |
0.522 |
|
| 1987 |
Colinge JP. Voltage-controlled bipolar-MOS (VCBM) ring oscillator Electronics Letters. 23: 1023-1025. DOI: 10.1049/El:19870717 |
0.439 |
|
| 1986 |
Kamins TI, Colinge JP. Thickness determination for silicon-on-insulator structures Electronics Letters. 22: 1236-1237. DOI: 10.1049/El:19860847 |
0.429 |
|
| 1986 |
Colinge JP. Half-micrometre-base lateral bipolar transistors made in thin silicon-on-insulator films Electronics Letters. 22: 886-887. DOI: 10.1049/El:19860604 |
0.493 |
|
| 1985 |
Colinge JP, Hu HK, Peng S. Fabrication of thin silicon-on-insulator flims using laser recrystallisation Electronics Letters. 21: 1102-1103. DOI: 10.1049/El:19850782 |
0.309 |
|
| 1984 |
Colinge JP. Laser Recrystallization and 3D Integration Mrs Proceedings. 35: 653. DOI: 10.1557/Proc-35-653 |
0.391 |
|
| 1984 |
Vu DP, Leguet C, Haond M, Bensahel D, Colinge JP. CMOS circuits made in lamp-recrystallised silicon-on-insulator Electronics Letters. 20: 298-299. DOI: 10.1049/El:19840204 |
0.448 |
|
| 1983 |
Colinge JP, Bensahel D, Alamome M, Haond M, Leguet C. Beam-Recrystallized Device-Worthy Films of Si on SiO2 via Control of the Grain Boundary Location Mrs Proceedings. 23. DOI: 10.1557/Proc-23-597 |
0.357 |
|
| 1983 |
Colinge J. Beam-recrystallised silicon-on-insulator films: can devices lives with grain boundaries? Microelectronics Journal. 14: 58-65. DOI: 10.1016/S0026-2692(83)80085-8 |
0.474 |
|
| 1982 |
Morel H, Colinge JP, Chante JP. Modelisation De Transistors Mos Réalisés Dans Du Silicium Polycristallin A Gros Grains Le Journal De Physique Colloques. 43. DOI: 10.1051/Jphyscol:1982151 |
0.303 |
|
| 1981 |
Colinge JP, Demoulin E. A high density CMOS inverter with stacked transistors Ieee Electron Device Letters. 2: 250-251. DOI: 10.1109/Edl.1981.25421 |
0.458 |
|
| Show low-probability matches. |