Chirag S. Patel, Ph.D.
Affiliations: | 2001 | Georgia Institute of Technology, Atlanta, GA |
Area:
Microelectronics/MicrosystemsGoogle:
"Chirag Patel"Mean distance: 20.07
Parents
Sign in to add mentor| James D. Meindl | grad student | 2001 | Georgia Tech | |
| (Compliant wafer level package (CWLP).) | ||||
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Publications
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| Dang B, Shih DY, Buchwalter S, et al. (2008) 50μm pitch Pb-free micro-bumps by C4NP technology Proceedings - Electronic Components and Technology Conference. 1505-1510 |
| Patel CS. (2006) Silicon carrier for computer systems Proceedings - Design Automation Conference. 857-862 |
| Dang B, Bakir MS, Patel CS, et al. (2006) Sea-of-Leads MEMS I/O interconnects for low-k IC packaging Journal of Microelectromechanical Systems. 15: 523-530 |
| Gan H, Wright SL, Polastre R, et al. (2006) Pb-free micro-joints (50 μm pitch) for the next generation micro-systems: The fabrication, assembly and characterization Proceedings - Electronic Components and Technology Conference. 2006: 1210-1215 |
| Andry PS, Tsang C, Sprogis E, et al. (2006) A CMOS-compatible process for fabricating electrical through-vias in silicon Proceedings - Electronic Components and Technology Conference. 2006: 831-837 |
| Knickerbocker JU, Andry PS, Buchwalter LP, et al. (2005) Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection Ibm Journal of Research and Development. 49: 725-753 |
| Roth B, Patel C. (2004) Application of Genetic Algorithms in the Engine Technology Selection Process Journal of Engineering For Gas Turbines and Power-Transactions of the Asme. 126: 693-700 |
| Dang B, Patel C, Thacker H, et al. (2004) Optimal implementation of sea of leads (SoL) compliant interconnect technology Proceedings of the Ieee 2004 International Interconnect Technology Conference. 99-101 |
| Keezer DC, Patel CS, Bakir MS, et al. (2003) Electrical test strategies for a wafer-level packaging technology [Abstracts of Forthcoming Manuscripts] Ieee Transactions On Electronics Packaging Manufacturing. 26: 264-264 |
| Keezer DC, Patel CS, Bakir MS, et al. (2003) Electrical test strategies for a wafer-level packaging technology Ieee Transactions On Electronics Packaging Manufacturing. 26: 267-272 |