Rohit S. Shenoy, Ph.D. - Publications

Affiliations: 
2005 Stanford University, Palo Alto, CA 

44 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2015 Burr GW, Shelby RM, Sidler S, di Nolfo C, Jang J, Boybat I, Shenoy RS, Narayanan P, Virwani K, Giacometti EU, Kurdi BN, Hwang H. Experimental Demonstration and Tolerancing of a Large-Scale Neural Network (165 000 Synapses) Using Phase-Change Memory as the Synaptic Weight Element Ieee Transactions On Electron Devices. DOI: 10.1109/TED.2015.2439635  1
2015 Padilla A, Burr GW, Shenoy RS, Raman KV, Bethune DS, Shelby RM, Rettner CT, Mohammad J, Virwani K, Narayanan P, Deb AK, Pandey RK, Bajaj M, Murali KVRM, Kurdi BN, et al. On the origin of steep i - V nonlinearity in mixed-ionic-electronic-conduction-based access devices Ieee Transactions On Electron Devices. 62: 963-971. DOI: 10.1109/TED.2015.2389832  1
2015 Narayanan P, Burr GW, Shenoy RS, Stephens S, Virwani K, Padilla A, Kurdi BN, Gopalakrishnan K. Exploring the design space for crossbar arrays built with mixed-ionic-electronic-conduction (MIEC) access devices Ieee Journal of the Electron Devices Society. 3: 423-434. DOI: 10.1109/JEDS.2015.2442242  1
2015 Narayanan P, Burr GW, Shenoy RS, Virwani K, Kurdi B. Circuit-level benchmarking of access devices for resistive nonvolatile memory arrays Technical Digest - International Electron Devices Meeting, Iedm. 2015: 29.7.1-29.7.4. DOI: 10.1109/IEDM.2014.7047137  1
2015 Burr GW, Shelby RM, Di Nolfo C, Jang JW, Shenoy RS, Narayanan P, Virwani K, Giacometti EU, Kurdi B, Hwang H. Experimental demonstration and tolerancing of a large-scale neural network (165,000 synapses), using phase-change memory as the synaptic weight element Technical Digest - International Electron Devices Meeting, Iedm. 2015: 29.5.1-29.5.4. DOI: 10.1109/IEDM.2014.7047135  1
2014 Cheng HY, Raoux S, Nguyen KV, Shenoy RS, BrightSky M. Ga46Sb54 material for fast switching and Pb-Free soldering reflow process complying phase-change memory Ecs Journal of Solid State Science and Technology. 3: P263-P267. DOI: 10.1149/2.011407jss  1
2014 Burr GW, Shenoy RS, Virwani K, Narayanan P, Padilla A, Kurdi B, Hwang H. Access devices for 3D crosspoint memory Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures. 32. DOI: 10.1116/1.4889999  1
2014 Narayanan P, Burr GW, Shenoy RS, Stephens S, Virwani K, Padilla A, Kurdi B, Gopalakrishnan K. Exploring the design space for resistive nonvolatile memory crossbar arrays with mixed ionic-electronic-conduction (MIEC)-based Access Devices Device Research Conference - Conference Digest, Drc. 239-240. DOI: 10.1109/DRC.2014.6872386  1
2014 Padilla A, Burr GW, Shenoy RS, Raman KV, Bethune D, Shelby RM, Rettner CT, Mohammad J, Virwani K, Narayanan P, Deb AK, Pandey RK, Bajaj M, Murali KVRM, Kurdi BN, et al. The origin of massive nonlinearity in Mixed-Ionic-Electronic-Conduction (MIEC)-based Access Devices, as revealed by numerical device simulation Device Research Conference - Conference Digest, Drc. 163-164. DOI: 10.1109/DRC.2014.6872348  1
2014 Shenoy RS, Burr GW, Virwani K, Jackson B, Padilla A, Narayanan P, Rettner CT, Shelby RM, Bethune DS, Raman KV, Brightsky M, Joseph E, Rice PM, Topuria T, Kellock AJ, et al. MIEC (mixed-ionic-electronic-conduction)-based access devices for non-volatile crossbar memory arrays Semiconductor Science and Technology. 29. DOI: 10.1088/0268-1242/29/10/104005  1
2013 Jackson BL, Rajendran B, Corrado GS, Breitwisch M, Burr GW, Cheek R, Gopalakrishnan K, Raoux S, Rettner CT, Padilla A, Schrott AG, Shenoy RS, Kurdi BN, Lam CH, Modha DS. Nanoscale electronic synapses using phase change devices Acm Journal On Emerging Technologies in Computing Systems. 9. DOI: 10.1145/2463585.2463588  1
2013 Burr GW, Virwani K, Shenoy RS, Fraczak G, Rettner CT, Padilla A, King RS, Nguyen K, Bowers AN, Jurich M, Brightsky M, Joseph EA, Kellock AJ, Arellano N, Kurdi BN, et al. Recovery dynamics and fast (sub-50ns) read operation with Access Devices for 3D crosspoint memory based on mixed-ionic-electronic-conduction (MIEC) Digest of Technical Papers - Symposium On Vlsi Technology. T66-T67.  1
2012 Burr GW, Virwani K, Shenoy RS, Padilla A, BrightSky M, Joseph EA, Lofaro M, Kellock AJ, King RS, Nguyen K, Bowers AN, Jurich M, Rettner CT, Jackson B, Bethune DS, et al. Large-scale (512kbit) integration of multilayer-ready access-devices based on Mixed-Ionic-Electronic-Conduction (MIEC) at 100% yield Digest of Technical Papers - Symposium On Vlsi Technology. 41-42. DOI: 10.1109/VLSIT.2012.6242451  1
2012 Virwani K, Burr GW, Shenoy RS, Rettner CT, Padilla A, Topuria T, Rice PM, Ho G, King RS, Nguyen K, Bowers AN, Jurich M, Brightsky M, Joseph EA, Kellock AJ, et al. Sub-30nm scaling and high-speed operation of fully-confined Access-Devices for 3D crosspoint memory based on mixed-ionic-electronic-conduction (MIEC) materials Technical Digest - International Electron Devices Meeting, Iedm. 2.7.1-2.7.4. DOI: 10.1109/IEDM.2012.6478967  1
2011 Padilla A, Burr GW, Rettner CT, Topuria T, Rice PM, Jackson B, Virwani K, Kellock AJ, Dupouy D, Debunne A, Shelby RM, Gopalakrishnan K, Shenoy RS, Kurdi BN. Voltage polarity effects in Ge2Sb2Te 5-based phase change memory devices Journal of Applied Physics. 110. DOI: 10.1063/1.3626047  1
2011 Shenoy RS, Gopalakrishnan K, Jackson B, Virwani K, Burr GW, Rettner CT, Padilla A, Bethune DS, Shelby RM, Kellock AJ, Breitwisch M, Joseph EA, Dasaka R, King RS, Nguyen K, et al. Endurance and scaling trends of novel access-devices for multi-layer crosspoint-memory based on mixed-ionic-electronic-conduction (MIEC) materials Digest of Technical Papers - Symposium On Vlsi Technology. 94-95.  1
2011 Choi S, Saeedifard M, Shenoy R. A modern educational power electronics laboratory to enhance hands-on active learning Asee Annual Conference and Exposition, Conference Proceedings 1
2010 Burr GW, Breitwisch MJ, Franceschini M, Garetto D, Gopalakrishnan K, Jackson B, Kurdi B, Lam C, Lastras LA, Padilla A, Rajendran B, Raoux S, Shenoy RS. Phase change memory technology Journal of Vacuum Science and Technology B:Nanotechnology and Microelectronics. 28: 223-262. DOI: 10.1116/1.3301579  1
2010 Gopalakrishnan K, Shenoy RS, Rettner CT, Virwani K, Bethune DS, Shelby RM, Burr GW, Kellock A, King RS, Nguyen K, Bowers AN, Jurich M, Jackson B, Friz AM, Topuria T, et al. Highly scalable novel access device based on Mixed Ionic Electronic Conduction (MIEC) materials for high density phase change memory (PCM) arrays Digest of Technical Papers - Symposium On Vlsi Technology. 205-206. DOI: 10.1109/VLSIT.2010.5556229  1
2010 Padilla A, Burr GW, Virwani K, Debunne A, Rettner CT, Topuria T, Rice PM, Jackson B, Dupouy D, Kellock AJ, Shelby RM, Gopalakrishnan K, Shenoy RS, Kurdi BN. Voltage polarity effects in GST-based phase change memory: Physical origins and implications Technical Digest - International Electron Devices Meeting, Iedm. 29.4.1-29.4.4. DOI: 10.1109/IEDM.2010.5703444  1
2010 Burr GW, Padilla A, Franceschini M, Jackson B, Dupouy DG, Rettner CT, Gopalakrishnan K, Shenoy R, Karidis J. The inner workings of phase change memory: Lessons from prototype PCM devices 2010 Ieee Globecom Workshops, Gc'10. 1890-1894. DOI: 10.1109/GLOCOMW.2010.5700271  1
2008 Cherian V, Shenoy R, Stothert A, Shriver J, Ghidella J, Gillespie TD. Model-based design of a SUV anti-rollover control system Sae Technical Papers. DOI: 10.4271/2008-01-0579  1
2008 Mahapatra S, Egel T, Hassan R, Shenoy R, Carone M. Model-based design for hybrid electric vehicle systems Sae Technical Papers. DOI: 10.4271/2008-01-0085  1
2008 Burr GW, Kurdi BN, Scott JC, Lam CH, Gopalakrishnan K, Shenoy RS. Overview of candidate device technologies for storage-class memory Ibm Journal of Research and Development. 52: 449-464. DOI: 10.1147/rd.524.0449  1
2008 Schmid GM, Khusnatdinov N, Brooks CB, LaBrake D, Thompson E, Resnick DJ, Owens J, Ford A, Sasaki S, Toyama N, Kurihara M, Hayashi N, Kobayashi H, Sato T, Nagarekawa O, ... ... Shenoy R, et al. Controlling linewidth roughness in step and flash imprint lithography Proceedings of Spie - the International Society For Optical Engineering. 6792. DOI: 10.1117/12.798936  1
2008 Khusnatdinov N, Schmid GM, Brooks CB, LaBrake D, Resnick DJ, Hart MW, Gopalakrishnan K, Shenoy R, Jih R, Zhang Y, Sikorski E, Rothwell MB, Owens J, Ford A. Minimizing linewidth roughness in Step and Flash Imprint Lithography Microelectronic Engineering. 85: 856-860. DOI: 10.1016/j.mee.2008.01.041  1
2008 Jardin MR, Shenoy R. Introducing the Model-Based Aerospace Challenge (MACH) Aiaa Guidance, Navigation and Control Conference and Exhibit 1
2008 Shenoy R, Jardin MR. Model-Based Aerospace Challenge 2 (MACH-2) Aiaa Guidance, Navigation and Control Conference and Exhibit 1
2007 Rajendran B, Shenoy RS, Witte DJ, Chokshi NS, DeLeon RL, Tompa GS, Pease RFW. Low thermal budget processing for sequential 3-D IC fabrication Ieee Transactions On Electron Devices. 54: 707-714. DOI: 10.1109/TED.2007.891300  1
2007 Kapur P, Shenoy RS, Saraswat KC. Power/performance based scalability comparisons between conventional and novel transistors down to 32nm technology node International Conference On Simulation of Semiconductor Processes and Devices, Sispad. 290-293. DOI: 10.1109/SISPAD.2006.282893  1
2007 Popinchalk S, Glass J, Shenoy R, Aberg R. Working in teams: Modeling and control design within a single software environment Collection of Technical Papers - 2007 Aiaa Modeling and Simulation Technologies Conference. 2: 1155-1178.  1
2006 Saraswat KC, Chui CO, Kapur P, Krishnamohan T, Nayfeh A, Okyay AK, Shenoy RS. Performance limitations of Si CMOS and alternatives for nanoelectronics International Journal of High Speed Electronics and Systems. 16: 175-192. DOI: 10.1142/S0129156406003606  1
2006 Shenoy RS, Gopalakrishnan K, Rettner CT, Bozano LD, King RS, Kurdi B, Wickramasinghe HK. A new route to ultra-high density memory using the Micro to Nano Addressing Block (MNAB) Digest of Technical Papers - Symposium On Vlsi Technology. 140-141.  1
2006 Stothert A, Shenoy R, Carone M. Interactive graphical tools for controller design Proceedings of the Ieee Conference On Decision and Control. 4570-4578.  1
2006 Denary T, Ghidella JR, Mosterman PJ, Shenoy R. Creating flight simulator landing gear models using multidomain modeling tools Collection of Technical Papers - Aiaa Modeling and Simulation Technologies Conference, 2006. 2: 1371-1382.  1
2005 Kekatpure RD, Brongersma ML, Shenoy RS. Design of a silicon-based field-effect electro-optic modulator with enhanced light-charge interaction. Optics Letters. 30: 2149-51. PMID 16127939 DOI: 10.1364/OL.30.002149  1
2005 Gopalakrishnan K, Woo R, Shenoy R, Jono Y, Griffin PB, Plummer JD. Novel very high IE structures based on the directed BBHE mechanism for ultralow-power flash memories Ieee Electron Device Letters. 26: 212-215. DOI: 10.1109/LED.2005.843784  1
2005 Chao AK, Kapur P, Shenoy RS, Nishi Y, Saraswat KC. Incorporation of supply voltage and process variations in the power optimization for future transistors Device Research Conference - Conference Digest, Drc. 2005: 95-96. DOI: 10.1109/DRC.2005.1553072  1
2005 Mosterman PJ, Shenoy R, Ghidella JR, Murphy B. Model-based design for test vector verification Autotestcon (Proceedings). 2005: 628-634. DOI: 10.1109/AUTEST.2005.1609209  1
2005 Gopalakrishnan K, Shenoy RS, Rettner CT, King RS, Zhang Y, Kurdi B, Bozano LD, Welser JJ, Rothwell ME, Jurich M, Sanchez MI, Hernandez M, Rice PM, Risk WP, Wickramasinghe HK. The Micro to Nano Addressing Block (MNAB) Technical Digest - International Electron Devices Meeting, Iedm. 2005: 471-474.  1
2005 Rajendran B, Shenoy RS, Witte DJ, Chokshi NS, DeLeon RL, Tompa GS, Pease RFW. CMOS transistor processing compatible with monolithic 3-D integration 2005 Proceedings - 22nd International Vlsi Multilevel Interconnection Conference, Vmic 2005. 76-82.  1
2004 Shenoy RS, Saraswat KC. Novel process for fully self-aligned planar ultrathin body double gate FET Proceedings - Ieee International Soi Conference. 190-191.  1
2004 Kapur P, Shenoy RS, Chao AK, Nishi Y, Saraswat KC. Power optimization of future transistors and a resulting global comparison standard Technical Digest - International Electron Devices Meeting, Iedm. 415-418.  1
2003 Shenoy RS, Saraswat KC. Optimization of extrinsic source/drain resistance in ultrathin body double-gate FETs Ieee Transactions On Nanotechnology. 2: 265-270. DOI: 10.1109/TNANO.2003.820780  1
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