| Year |
Citation |
Score |
| 2017 |
Kurdahi F, Faruque MAA, Gajski D, Eltawil A. A case study to develop a graduate-level degree program in embedded & cyber-physical systems Acm Sigbed Review. 14: 16-21. DOI: 10.1145/3036686.3036688 |
0.312 |
|
| 2015 |
He W, Gajski D, Farkas G, Warschauer M. Implementing flexible hybrid instruction in an electrical engineering course: The best of three worlds? Computers and Education. 81: 59-68. DOI: 10.1016/J.Compedu.2014.09.005 |
0.326 |
|
| 2010 |
Viskic I, Yu L, Gajski D. Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications Proceedings of the Acm Sigplan Conference On Languages, Compilers, and Tools For Embedded Systems (Lctes). 77-84. DOI: 10.1145/1755888.1755900 |
0.448 |
|
| 2010 |
Trajkovic J, Gajski DD. Early performance-cost estimation of application-specific data path pipelining Proceedings of the 2010 Ieee 8th Symposium On Application Specific Processors, Sasp'10. 107-110. DOI: 10.1109/SASP.2010.5521136 |
0.346 |
|
| 2009 |
Abdi S, Gajski DD, Viskic I. Model based synthesis of embedded software Journal of Software. 4: 717-727. DOI: 10.4304/Jsw.4.7.717-727 |
0.709 |
|
| 2009 |
Yu Lo LLC, Abdi S, Gajski D. Transaction level model automation for multicore systems Behavioral Modeling For Embedded Systems and Technologies: Applications For Design and Implementation. 271-289. DOI: 10.4018/978-1-60566-750-8.ch011 |
0.633 |
|
| 2009 |
Coussy P, Gajski DD, Meredith M, Takach A. An introduction to high-level synthesis Ieee Design and Test of Computers. 26: 8-17. DOI: 10.1109/MDT.2009.69 |
0.348 |
|
| 2009 |
Gajski D, Abdi S. Transaction-level system modeling Practical Design Verification. 51-91. DOI: 10.1017/CBO9780511626913.002 |
0.611 |
|
| 2009 |
Gajski DD. System-level synthesis: From specification to transaction level models 2009 International Conference On Communications, Circuits and Systems, Icccas 2009. 1134-1138. |
0.376 |
|
| 2008 |
Gorjiara B, Reshadi M, Gajski D. Merged Dictionary Code Compression for FPGA Implementation of Custom Microcoded PEs Acm Transactions On Reconfigurable Technology and Systems. 1: 11. DOI: 10.1145/1371579.1371583 |
0.787 |
|
| 2008 |
Shin D, Gerstlauer A, Domer R, Gajski DD. An interactive design environment for C-based high-level synthesis of RTL processors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 466-475. DOI: 10.1109/Tvlsi.2007.915390 |
0.767 |
|
| 2008 |
Trajkovic J, Gajski DD. Custom processor core construction from C code 2008 Symposium On Application Specific Processors, Sasp 2008. 1-6. DOI: 10.1109/SASP.2008.4570778 |
0.438 |
|
| 2008 |
Hwang Y, Abdi S, Gajski D. Cycle-approximate retargetable performance estimation at the transaction level Proceedings -Design, Automation and Test in Europe, Date. 3-8. DOI: 10.1109/DATE.2008.4484651 |
0.592 |
|
| 2008 |
Gorjiara B, Gajski D. Automatic architecture refinement techniques for customizing processing elements Proceedings - Design Automation Conference. 379-384. DOI: 10.1109/DAC.2008.4555847 |
0.815 |
|
| 2008 |
Reshadi M, Gorjara B, Gajski D. C-based design flow: A case study on G.729A for voice over internet protocol (VoIP) Proceedings - Design Automation Conference. 72-75. DOI: 10.1109/DAC.2008.4555784 |
0.699 |
|
| 2008 |
Gorjiara B, Reshadi M, Gajski D. GNR: A Formal Language for Specification, Compilation, and Synthesis of Custom Embedded Processors Processor Description Languages. 329-367. DOI: 10.1016/B978-012374287-2.50016-1 |
0.803 |
|
| 2008 |
Gajski DD. System level design: Past, present, and future Design, Automation, and Test in Europe: the Most Influential Papers of 10 Years Date. 3-14. DOI: 10.1007/978-1-4020-6488-3_1 |
0.387 |
|
| 2007 |
Viskic I, Abdi S, Gajski DD. Automatic generation of embedded communication SW for heterogeneous MPSoC platforms Proceedings of the Acm Sigplan Conference On Languages, Compilers, and Tools For Embedded Systems (Lctes). 143-145. DOI: 10.1145/1254766.1254792 |
0.567 |
|
| 2007 |
Cho H, Abdi S, Gajski D. Interface synthesis for heterogeneous multi-core systems from transaction level models Proceedings of the Acm Sigplan Conference On Languages, Compilers, and Tools For Embedded Systems (Lctes). 140-142. DOI: 10.1145/1254766.1254791 |
0.668 |
|
| 2007 |
Gorjiara B, Gajski D. FPGA-friendly code compression for horizontal microcoded custom IPs Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 108-115. DOI: 10.1145/1216919.1216935 |
0.747 |
|
| 2007 |
Gajski DD. New strategies for system level design 2006 International Symposium On Vlsi Design, Automation and Test, Vlsi-Dat 2006 - Proceedings of Technical Papers. 1-5. DOI: 10.1109/VDAT.2006.258106 |
0.303 |
|
| 2007 |
Gorjiara B, Gajski D. A novel profile-driven technique for simultaneous power and code-size optimization of microcoded IPs 2007 Ieee International Conference On Computer Design, Iccd 2007. 609-614. DOI: 10.1109/ICCD.2007.4601960 |
0.74 |
|
| 2007 |
Gajski DD. New strategies for system design Proceedings - 2007 International Conference On Design and Technology of Integrated Systems in Nanoscale Era, Dtis 2007. DOI: 10.1109/DTIS.2007.4449481 |
0.476 |
|
| 2007 |
Gajski DD. New strategies for system-level design Proceedings of the 2007 Ieee Workshop On Design and Diagnostics of Electronic Circuits and Systems, Ddecs. 15. DOI: 10.1109/DDECS.2007.4295246 |
0.456 |
|
| 2007 |
Reshadi M, Gajski D. Interrupt and low-level programming support for expanding the application domain of statically-scheduled horizontal-microcoded architectures in embedded systems Proceedings -Design, Automation and Test in Europe, Date. 1337-1342. DOI: 10.1109/DATE.2007.364483 |
0.748 |
|
| 2007 |
Gorjiara B, Reshadi M, Gajski D. Low-power design with NISC technology Designing Embedded Processors: a Low Power Perspective. 25-50. DOI: 10.1007/978-1-4020-5869-1_2 |
0.789 |
|
| 2007 |
Trajkovic J, Gajski D. Automatic data path generation from C code for custom processors Ifip International Federation For Information Processing. 231: 107-120. DOI: 10.1007/978-0-387-72258-0_10 |
0.425 |
|
| 2006 |
Gorjiara B, Reshadi M, Chandraiah P, Gajski D. Generic netlist representation for system and PE level design exploration Codes+Isss 2006: Proceedings of the 4th International Conference On Hardware Software Codesign and System Synthesis. 282-287. DOI: 10.1145/1176254.1176323 |
0.813 |
|
| 2006 |
Gorjiara B, Reshadi M, Gajski D. Generic architecture description for retargetable compilation and synthesis of application-specific pipelined IPs Ieee International Conference On Computer Design, Iccd 2006. 356-361. DOI: 10.1109/ICCD.2006.4380841 |
0.82 |
|
| 2006 |
Abdi S, Gajski D. Transaction routing and its verification by correct model transformations Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 129-136. DOI: 10.1109/HLDVT.2006.319975 |
0.551 |
|
| 2006 |
Trajkovic J, Reshadi M, Gorjiara B, Gajski D. A graph based algorithm for data path optimization in custom processors Proceedings of the 9th Euromicro Conference On Digital System Design: Architectures, Methods and Tools, Dsd 2006. 496-503. DOI: 10.1109/DSD.2006.7 |
0.805 |
|
| 2006 |
Abdi S, Gajski D. Verification of system level model transformations International Journal of Parallel Programming. 34: 29-59. DOI: 10.1007/S10766-005-0001-Y |
0.611 |
|
| 2006 |
Cho H, Abdi S, Gajski D. Design and implementation of transducer for ARM-TMS communication Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2006: 126-127. |
0.603 |
|
| 2006 |
Gorjiara B, Reshadi M, Gajski D. Designing a custom architecture for DCT using NISC technology Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2006: 116-117. |
0.806 |
|
| 2005 |
Gajski DD. System design extreme makeover Proceedings - Third Acm and Ieee International Conference On Formal Methods and Models For Co-Design, Memocode'05. 2005: 71-76. DOI: 10.1109/MEMCOD.2005.1487895 |
0.326 |
|
| 2005 |
Reshadi M, Gorjiara B, Gajski D. Utilizing horizontal and vertical parallelism with a no-instruction-set compiler for custom datapaths Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 2005: 69-74. DOI: 10.1109/ICCD.2005.112 |
0.793 |
|
| 2005 |
Gorjiara B, Gajski D. Custom processor design using NISC: A case-study on DCT algorithm Proceedings of the 2005 3rd Workshop On Embedded Systems For Real-Time Multimedia. 2005: 55-60. DOI: 10.1109/ESTMED.2005.1518072 |
0.824 |
|
| 2005 |
Abdi S, Gajski D. Functional validation of system level static scheduling Proceedings -Design, Automation and Test in Europe, Date '05. 542-547. DOI: 10.1109/DATE.2005.164 |
0.563 |
|
| 2005 |
Abdi S, Gajski D. A formalism for functionality preserving system level transformations Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 1: 139-144. |
0.598 |
|
| 2005 |
Reshadi M, Gajski D. A cycle-accurate compilation algorithm for custom pipelined datapaths Codes+Isss 2005 - International Conference On Hardware/Software Codesign and System Synthesis. 21-26. |
0.742 |
|
| 2005 |
Yu H, Dömer R, Gajski DD. Software and driver synthesis from transaction level models Ifip Advances in Information and Communication Technology. 184: 65-76. |
0.325 |
|
| 2005 |
Peng J, Abdi S, Gajski D. A clustering technique to optimize hardware/software synchronization Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2: 965-968. |
0.59 |
|
| 2005 |
Cai L, Gerstlauer A, Gajski D. Multi-metric and multi-entity characterization of applications for early system design exploration Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2: 944-947. |
0.672 |
|
| 2004 |
Abdi S, Gajski D. Model validation for mapping specification behaviors to processing elements Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 101-106. DOI: 10.1109/HLDVT.2004.1431247 |
0.572 |
|
| 2004 |
Abdi S, Gajski D. Automatic generation of equivalent architecture model from functional specification Proceedings - Design Automation Conference. 608-613. |
0.573 |
|
| 2004 |
Abdi S, Gajski D. On deriving equivalent architecture model from system specification Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 322-327. |
0.601 |
|
| 2004 |
Yu H, Dömer R, Gajski D. Embedded software generation from system level design languages Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 463-468. |
0.457 |
|
| 2004 |
Cai L, Gerstlauer A, Gajski D. Retargetable profiling for rapid, early system-level design space exploration Proceedings - Design Automation Conference. 281-286. |
0.651 |
|
| 2004 |
Shin D, Abdi S, Gajski DD. Automatic generation of bus functional models from transaction level models Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 756-758. |
0.6 |
|
| 2003 |
Yu H, Gerstlauer A, Gajski D. RTOS Scheduling in Transaction Level Models Hardware/Software Codesign - Proceedings of the International Workshop. 31-36. DOI: 10.1145/944645.944653 |
0.693 |
|
| 2003 |
Gai L, Gajski D. Transaction Level Modeling: An Overview Hardware/Software Codesign - Proceedings of the International Workshop. 19-24. |
0.326 |
|
| 2003 |
Abdi S, Shin D, Gajski D. Automatic communication refinement for system level design Proceedings - Design Automation Conference. 300-305. |
0.578 |
|
| 2002 |
Saoud SB, Gajski DD, Gerstlauer A. Co-design of emulators for power electric processes using SpecC methodology Iecon Proceedings (Industrial Electronics Conference). 3: 2143-2148. DOI: 10.1109/IECON.2002.1185304 |
0.714 |
|
| 2002 |
Saoud SB, Gajski DD. Design of real-time emulators of electromechanical systems Powercon 2002 - 2002 International Conference On Power System Technology, Proceedings. 2: 828-833. DOI: 10.1109/ICPST.2002.1047515 |
0.436 |
|
| 2002 |
Cai L, Kritzinger P, Olivares M, Gajski D. Top-down system level design methodology using SpecC, VCC and SystemC Proceedings -Design, Automation and Test in Europe, Date. 1137. DOI: 10.1109/DATE.2002.998495 |
0.395 |
|
| 2002 |
Peng J, Abdi S, Gajski D. Automatic model refinement for fast architecture exploration [SoC design] Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference On Vlsi Design, Asp-Dac/Vlsi Design 2002. 332-337. DOI: 10.1109/ASPDAC.2002.994944 |
0.676 |
|
| 2002 |
Peng J, Gajski D. Optimal message-passing for data coherency in distributed architecture Proceedings of the International Symposium On System Synthesis. 20-25. |
0.361 |
|
| 2002 |
Gerstlauer A, Gajski DD. System-level abstraction semantics Proceedings of the International Symposium On System Synthesis. 231-236. |
0.68 |
|
| 2002 |
Ben Saoud S, Gajski DD, Gerstlauer A. Seamless approach for the design of control systems for power electronics and electric drives Proceedings of the Ieee International Conference On Systems, Man and Cybernetics. 6: 379-384. |
0.673 |
|
| 2002 |
Saoud SB, Gajski DD, Gerstlauer A. Co-design of embedded controllers for power electronics and electric systems Ieee International Symposium On Intelligent Control - Proceedings. 379-383. |
0.663 |
|
| 2001 |
Zhu J, Gajski DD. Compiling SpecC for simulation Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2001: 57-62. DOI: 10.1109/ASPDAC.2001.913281 |
0.4 |
|
| 2001 |
Cai L, Gajski D, Olivarez M. Introduction of system level architecture exploration using the SpecC methodology Proceedings - Ieee International Symposium On Circuits and Systems. 5: 9-12. |
0.444 |
|
| 2001 |
Bakshi S, Gajski DD. Performance-constrained hierarchical pipelining for behaviors, loops, and operations Acm Transactions On Design Automation of Electronic Systems. 6: 1-25. |
0.338 |
|
| 1999 |
Bakshi S, Gajski DD. Partitioning and pipelining for performance-constrained hardware/software systems Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 7: 419-432. DOI: 10.1109/92.805749 |
0.484 |
|
| 1999 |
Zhu J, Gajski DD. Unified formal model of ISA and FSMD Hardware/Software Codesign - Proceedings of the International Workshop. 121-125. |
0.366 |
|
| 1998 |
Gajski DD, Vahid F, Narayan S, Gong J. SpecSyn: An environment supporting the specify-explore-refine paradigm for hardware/software system design Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 6: 84-100. DOI: 10.1109/92.661251 |
0.452 |
|
| 1998 |
Gajski DD, Vahid F, Narayan S, Gong J. System-level exploration with SpecSyn Proceedings - Design Automation Conference. 812-817. |
0.383 |
|
| 1997 |
Bakshi S, Gajski DD. Scheduling and pipelining algorithm for hardware/software systems Proceedings of the International Symposium On System Synthesis. 113-118. |
0.399 |
|
| 1997 |
Bakshi S, Gajski DD. Hardware/software partitioning and pipelining Proceedings - Design Automation Conference. 713-719. |
0.441 |
|
| 1996 |
Gajski DD. Methodology is the future Ieee Asia-Pacific Conference On Circuits and Systems - Proceedings. 269-277. |
0.423 |
|
| 1996 |
Narayan S, Gajski DD. Rapid performance estimation for system design European Design Automation Conference - Proceedings. 206-211. |
0.388 |
|
| 1996 |
Chang ES, Gajski DD, Narayan S. An optimal clock period selection method based on slack minimization criteria Acm Transactions On Design Automation of Electronic Systems. 1: 352-370. |
0.359 |
|
| 1996 |
Gong J, Gajski DD, Bakshi S. Model refinement for hardware-software codesign Proceedings of European Design and Test Conference. 270-274. |
0.311 |
|
| 1996 |
Juan HP, Gajski DD, Chaiyakul V. Clock-driven performance optimization in interactive behavioral synthesis Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 154-157. |
0.348 |
|
| 1996 |
Bakshi S, Gajski DD, Juan HP. Component selection in resource shared and pipelined DSP applications European Design Automation Conference - Proceedings. 370-375. |
0.317 |
|
| 1996 |
Juan HP, Gajski DD, Bakshi S. Clock optimization for high-performance pipelined design European Design Automation Conference - Proceedings. 330-335. |
0.349 |
|
| 1995 |
Gong J, Gajski DD, Nicolau A. Performance Evaluation for Application-Specific Architectures Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 3: 483-490. DOI: 10.1109/92.475967 |
0.407 |
|
| 1995 |
Gajski DD, Vahid F. Specification and Design of Embedded Hardware-Software Systems Ieee Design and Test of Computers. 12: 53-67. DOI: 10.1109/54.350695 |
0.43 |
|
| 1995 |
Vahid F, Gajski DD. Closeness metrics for system-level functional partitioning European Design Automation Conference - Proceedings. 328-333. |
0.36 |
|
| 1994 |
Bakshi S, Gajski DD. Design exploration for high-performance pipelines Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 312-316. |
0.385 |
|
| 1994 |
Vahid F, Gong J, Gajski DD. Binary-constraint search algorithm for minimizing hardware during hardware/software partitioning European Design Automation Conference - Proceedings. 214-219. |
0.374 |
|
| 1994 |
Gong J, Gajski DD, Nicolau A. Performance evaluator for parameterized ASIC architectures European Design Automation Conference - Proceedings. 66-71. |
0.415 |
|
| 1994 |
Gajski DD, Vahid F, Narayan S. System-design methodology: Executable-specification refinement Proceedings of the European Design and Test Conference. 458-463. |
0.426 |
|
| 1993 |
Rundensteiner EA, Gajski DD, Bic L. Component Synthesis From Functional Descriptions Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 12: 1287-1299. DOI: 10.1109/43.240076 |
0.307 |
|
| 1993 |
Ramachandran L, Gajski DD. Architectural tradeoffs in synthesis of pipelined controls European Design Automation Conference - Proceedings. 244-249. |
0.395 |
|
| 1993 |
Narayan S, Gajski DD. Features supporting sytem-level specification in HDLs European Design Automation Conference - Proceedings. 540-545. |
0.343 |
|
| 1993 |
Chaiyakul V, Gajski DD, Ramachandran L. High-level transformations for minimizing syntactic variances Proceedings - Design Automation Conference. 413-418. |
0.391 |
|
| 1993 |
Juan HP, Holmes ND, Bakshi S, Gajski DD. Top-down modeling of RISC processors in VHDL European Design Automation Conference - Proceedings. 454-459. |
0.339 |
|
| 1992 |
Sanjiv N, Frank V, Gajski DD. System Specification with the SpecCharts Language Ieee Design and Test of Computers. 9: 6-13. DOI: 10.1109/54.173326 |
0.397 |
|
| 1992 |
Ramachandran L, Gajski DD. An algorithm for component selection in performance optimized scheduling 1991 Ieee International Conference On Computer-Aided Design Digest of Technical Papers. 92-95. |
0.347 |
|
| 1992 |
Narayan S, Gajski DD. System clock estimation based on clock slack minimization European Design Automation Conference. 66-71. |
0.312 |
|
| 1992 |
Vahid F, Gajski DD. Specification partitioning for system design Proceedings - Design Automation Conference. 219-224. |
0.331 |
|
| 1992 |
Rundensteiner EA, Gajski DD. Functional synthesis using area and delay optimization Proceedings - Design Automation Conference. 291-296. |
0.375 |
|
| 1992 |
Wu ACH, Hadley TS, Gajski DD. Efficient multi-view design model for real-time interactive synthesis Ieee/Acm International Conference On Computer-Aided Design. 328-331. |
0.411 |
|
| 1990 |
Dutt ND, Gajski DD. Design synthesis and silicon compilation Ieee Design and Test of Computers. 7: 8-23. DOI: 10.1109/54.64954 |
0.554 |
|
| 1990 |
Brewer F, Gajski D. Chippe: A System for Constraint Driven Behavioral Synthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 9: 681-695. DOI: 10.1109/43.55208 |
0.41 |
|
| 1989 |
Dutt ND, Gajski DD. Designer controlled behavioral synthesis Proceedings - Design Automation Conference. 754-757. |
0.349 |
|
| 1989 |
Lis JS, Gajski DD. VHDL synthesis using structured modeling Proceedings - Design Automation Conference. 606-609. |
0.366 |
|
| 1988 |
Lin YL, Gajski DD. LES: A Layout Expert System Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 7: 868-876. DOI: 10.1109/43.3218 |
0.387 |
|
| 1988 |
Lis JS, Gajski DD. Synthesis from VHDL . 378-381. |
0.312 |
|
| 1987 |
Pangrle BM, Gajski DD. Design Tools for Intelligent Silicon Compilation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 6: 1098-1112. DOI: 10.1109/TCAD.1987.1270350 |
0.401 |
|
| 1987 |
Pangrle BM, Gajski DD. SLICER: A STATE SYNTHESIZER FOR INTELLIGENT SILICON COMPILATION . 42-45. |
0.398 |
|
| 1985 |
Gajski DD. ARSENIC SILICON COMPILER Proceedings - Ieee International Symposium On Circuits and Systems. 399-402. |
0.355 |
|
| 1984 |
Kim W, Gajski D, Kuck DJ. A parallel pipelined relational query processor Acm Transactions On Database Systems (Tods). 9: 214-235. DOI: 10.1145/329.332 |
0.434 |
|
| 1983 |
Gajski D, Kuck D, Lawrie D, Sameh A. CEDAR: a large scale multiprocessor Acm Sigarch Computer Architecture News. 11: 7-11. DOI: 10.1145/859526.859527 |
0.399 |
|
| 1981 |
Casavant AE, Gajski DD, Kuck DJ. AUTOMATIC DESIGN WITH DEPENDENCE GRAPHS Jahrbuch Der Schiffbautechnischen Gesellschaft. 506-515. |
0.419 |
|
| 1977 |
Gajski DD. GSI IMPACT: LOGIC-DESIGN POINT OF VIEW . 312-326. |
0.353 |
|
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