| Year |
Citation |
Score |
| 2014 |
Kim K, Gajski DD. Hierarchy-Aware mapping of pipelined applications Midwest Symposium On Circuits and Systems. 631-634. DOI: 10.1109/MWSCAS.2014.6908494 |
1 |
|
| 2014 |
Kim K, Gajski DD. Trace-Driven Performance Estimation of multi-core platforms Midwest Symposium On Circuits and Systems. 627-630. DOI: 10.1109/MWSCAS.2014.6908493 |
1 |
|
| 2014 |
Dang QV, Gajski DD. Bringing in-class online - A hybrid solution Proceedings of the 4th Interdisciplinary Engineering Design Education Conference, Iedec 2014. 12-17. DOI: 10.1109/IEDEC.2014.6784674 |
1 |
|
| 2010 |
Gajski D, Austin T, Svoboda S. What input-language is the best choice for high level synthesis (HLS)? Proceedings - Design Automation Conference. 857-858. DOI: 10.1145/1837274.1837489 |
1 |
|
| 2010 |
Viskic I, Yu L, Gajski D. Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications Proceedings of the Acm Sigplan Conference On Languages, Compilers, and Tools For Embedded Systems (Lctes). 77-84. DOI: 10.1145/1755888.1755900 |
1 |
|
| 2010 |
Trajkovic J, Gajski DD. Early performance-cost estimation of application-specific data path pipelining Proceedings of the 2010 Ieee 8th Symposium On Application Specific Processors, Sasp'10. 107-110. DOI: 10.1109/SASP.2010.5521136 |
1 |
|
| 2009 |
Abdi S, Gajski DD, Viskic I. Model based synthesis of embedded software Journal of Software. 4: 717-727. DOI: 10.4304/Jsw.4.7.717-727 |
1 |
|
| 2009 |
Yu Lo LLC, Abdi S, Gajski D. Transaction level model automation for multicore systems Behavioral Modeling For Embedded Systems and Technologies: Applications For Design and Implementation. 271-289. DOI: 10.4018/978-1-60566-750-8.ch011 |
1 |
|
| 2009 |
Coussy P, Gajski DD, Meredith M, Takach A. An introduction to high-level synthesis Ieee Design and Test of Computers. 26: 8-17. DOI: 10.1109/MDT.2009.69 |
1 |
|
| 2009 |
Gajski D, Abdi S. Transaction-level system modeling Practical Design Verification. 51-91. DOI: 10.1017/CBO9780511626913.002 |
1 |
|
| 2009 |
Gajski DD. System-level synthesis: From specification to transaction level models 2009 International Conference On Communications, Circuits and Systems, Icccas 2009. 1134-1138. |
1 |
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| 2008 |
Gorjiara B, Reshadi M, Gajski D. Merged Dictionary Code Compression for FPGA Implementation of Custom Microcoded PEs Acm Transactions On Reconfigurable Technology and Systems. 1: 11. DOI: 10.1145/1371579.1371583 |
1 |
|
| 2008 |
Shin D, Gerstlauer A, Domer R, Gajski DD. An interactive design environment for C-based high-level synthesis of RTL processors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 466-475. DOI: 10.1109/Tvlsi.2007.915390 |
1 |
|
| 2008 |
Trajkovic J, Gajski DD. Custom processor core construction from C code 2008 Symposium On Application Specific Processors, Sasp 2008. 1-6. DOI: 10.1109/SASP.2008.4570778 |
1 |
|
| 2008 |
Hwang Y, Abdi S, Gajski D. Cycle-approximate retargetable performance estimation at the transaction level Proceedings -Design, Automation and Test in Europe, Date. 3-8. DOI: 10.1109/DATE.2008.4484651 |
1 |
|
| 2008 |
Gorjiara B, Gajski D. Automatic architecture refinement techniques for customizing processing elements Proceedings - Design Automation Conference. 379-384. DOI: 10.1109/DAC.2008.4555847 |
1 |
|
| 2008 |
Reshadi M, Gorjara B, Gajski D. C-based design flow: A case study on G.729A for voice over internet protocol (VoIP) Proceedings - Design Automation Conference. 72-75. DOI: 10.1109/DAC.2008.4555784 |
1 |
|
| 2008 |
Gorjiara B, Reshadi M, Gajski D. GNR: A Formal Language for Specification, Compilation, and Synthesis of Custom Embedded Processors Processor Description Languages. 329-367. DOI: 10.1016/B978-012374287-2.50016-1 |
1 |
|
| 2008 |
Gajski DD. System level design: Past, present, and future Design, Automation, and Test in Europe: the Most Influential Papers of 10 Years Date. 3-14. DOI: 10.1007/978-1-4020-6488-3_1 |
1 |
|
| 2007 |
Viskic I, Abdi S, Gajski DD. Automatic generation of embedded communication SW for heterogeneous MPSoC platforms Proceedings of the Acm Sigplan Conference On Languages, Compilers, and Tools For Embedded Systems (Lctes). 143-145. DOI: 10.1145/1254766.1254792 |
1 |
|
| 2007 |
Cho H, Abdi S, Gajski D. Interface synthesis for heterogeneous multi-core systems from transaction level models Proceedings of the Acm Sigplan Conference On Languages, Compilers, and Tools For Embedded Systems (Lctes). 140-142. DOI: 10.1145/1254766.1254791 |
1 |
|
| 2007 |
Gorjiara B, Gajski D. FPGA-friendly code compression for horizontal microcoded custom IPs Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 108-115. DOI: 10.1145/1216919.1216935 |
1 |
|
| 2007 |
Gajski DD. New strategies for system level design 2006 International Symposium On Vlsi Design, Automation and Test, Vlsi-Dat 2006 - Proceedings of Technical Papers. 1-5. DOI: 10.1109/VDAT.2006.258106 |
1 |
|
| 2007 |
Gorjiara B, Gajski D. A novel profile-driven technique for simultaneous power and code-size optimization of microcoded IPs 2007 Ieee International Conference On Computer Design, Iccd 2007. 609-614. DOI: 10.1109/ICCD.2007.4601960 |
1 |
|
| 2007 |
Gajski DD. New strategies for system design Proceedings - 2007 International Conference On Design and Technology of Integrated Systems in Nanoscale Era, Dtis 2007. DOI: 10.1109/DTIS.2007.4449481 |
1 |
|
| 2007 |
Gajski DD. New strategies for system-level design Proceedings of the 2007 Ieee Workshop On Design and Diagnostics of Electronic Circuits and Systems, Ddecs. 15. DOI: 10.1109/DDECS.2007.4295246 |
1 |
|
| 2007 |
Reshadi M, Gajski D. Interrupt and low-level programming support for expanding the application domain of statically-scheduled horizontal-microcoded architectures in embedded systems Proceedings -Design, Automation and Test in Europe, Date. 1337-1342. DOI: 10.1109/DATE.2007.364483 |
1 |
|
| 2007 |
Gorjiara B, Reshadi M, Gajski D. Low-power design with NISC technology Designing Embedded Processors: a Low Power Perspective. 25-50. DOI: 10.1007/978-1-4020-5869-1_2 |
1 |
|
| 2007 |
Trajkovic J, Gajski D. Automatic data path generation from C code for custom processors Ifip International Federation For Information Processing. 231: 107-120. DOI: 10.1007/978-0-387-72258-0_10 |
1 |
|
| 2006 |
Gorjiara B, Reshadi M, Chandraiah P, Gajski D. Generic netlist representation for system and PE level design exploration Codes+Isss 2006: Proceedings of the 4th International Conference On Hardware Software Codesign and System Synthesis. 282-287. DOI: 10.1145/1176254.1176323 |
1 |
|
| 2006 |
Gorjiara B, Reshadi M, Gajski D. Generic architecture description for retargetable compilation and synthesis of application-specific pipelined IPs Ieee International Conference On Computer Design, Iccd 2006. 356-361. DOI: 10.1109/ICCD.2006.4380841 |
1 |
|
| 2006 |
Abdi S, Gajski D. Transaction routing and its verification by correct model transformations Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 129-136. DOI: 10.1109/HLDVT.2006.319975 |
1 |
|
| 2006 |
Trajkovic J, Reshadi M, Gorjiara B, Gajski D. A graph based algorithm for data path optimization in custom processors Proceedings of the 9th Euromicro Conference On Digital System Design: Architectures, Methods and Tools, Dsd 2006. 496-503. DOI: 10.1109/DSD.2006.7 |
1 |
|
| 2006 |
Abdi S, Gajski D. Verification of system level model transformations International Journal of Parallel Programming. 34: 29-59. DOI: 10.1007/S10766-005-0001-Y |
1 |
|
| 2006 |
Cho H, Abdi S, Gajski D. Design and implementation of transducer for ARM-TMS communication Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2006: 126-127. |
1 |
|
| 2006 |
Gorjiara B, Reshadi M, Gajski D. Designing a custom architecture for DCT using NISC technology Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2006: 116-117. |
1 |
|
| 2005 |
Gajski DD. System design extreme makeover Proceedings - Third Acm and Ieee International Conference On Formal Methods and Models For Co-Design, Memocode'05. 2005: 71-76. DOI: 10.1109/MEMCOD.2005.1487895 |
1 |
|
| 2005 |
Reshadi M, Gorjiara B, Gajski D. Utilizing horizontal and vertical parallelism with a no-instruction-set compiler for custom datapaths Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 2005: 69-74. DOI: 10.1109/ICCD.2005.112 |
1 |
|
| 2005 |
Gorjiara B, Gajski D. Custom processor design using NISC: A case-study on DCT algorithm Proceedings of the 2005 3rd Workshop On Embedded Systems For Real-Time Multimedia. 2005: 55-60. DOI: 10.1109/ESTMED.2005.1518072 |
1 |
|
| 2005 |
Abdi S, Gajski D. Functional validation of system level static scheduling Proceedings -Design, Automation and Test in Europe, Date '05. 542-547. DOI: 10.1109/DATE.2005.164 |
1 |
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| 2005 |
Abdi S, Gajski D. A formalism for functionality preserving system level transformations Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 1: 139-144. |
1 |
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| 2005 |
Reshadi M, Gajski D. A cycle-accurate compilation algorithm for custom pipelined datapaths Codes+Isss 2005 - International Conference On Hardware/Software Codesign and System Synthesis. 21-26. |
1 |
|
| 2005 |
Zhao S, Gajski DD. Defining an enhanced RTL semantics Proceedings -Design, Automation and Test in Europe, Date '05. 548-553. |
1 |
|
| 2005 |
Zhao S, Gajski DD. Structural operational semantics for supporting multi-cycle operations in RTL HDLs Proceedings - Third Acm and Ieee International Conference On Formal Methods and Models For Co-Design, Memocode'05. 2005: 45-54. |
1 |
|
| 2005 |
Yu H, Dömer R, Gajski DD. Software and driver synthesis from transaction level models Ifip Advances in Information and Communication Technology. 184: 65-76. |
1 |
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| 2005 |
Peng J, Abdi S, Gajski D. A clustering technique to optimize hardware/software synchronization Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2: 965-968. |
1 |
|
| 2005 |
Cai L, Gerstlauer A, Gajski D. Multi-metric and multi-entity characterization of applications for early system design exploration Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2: 944-947. |
1 |
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| 2004 |
Abdi S, Gajski D. Model validation for mapping specification behaviors to processing elements Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 101-106. DOI: 10.1109/HLDVT.2004.1431247 |
1 |
|
| 2004 |
Abdi S, Gajski D. Automatic generation of equivalent architecture model from functional specification Proceedings - Design Automation Conference. 608-613. |
1 |
|
| 2004 |
Abdi S, Gajski D. On deriving equivalent architecture model from system specification Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 322-327. |
1 |
|
| 2004 |
Yu H, Dömer R, Gajski D. Embedded software generation from system level design languages Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 463-468. |
1 |
|
| 2004 |
Cai L, Yu H, Gajski D. A novel memory size model for variable-mapping in system level design Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 813-818. |
1 |
|
| 2004 |
Cai L, Gerstlauer A, Gajski D. Retargetable profiling for rapid, early system-level design space exploration Proceedings - Design Automation Conference. 281-286. |
1 |
|
| 2004 |
Shin D, Abdi S, Gajski DD. Automatic generation of bus functional models from transaction level models Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 756-758. |
1 |
|
| 2003 |
Yu H, Gerstlauer A, Gajski D. RTOS Scheduling in Transaction Level Models Hardware/Software Codesign - Proceedings of the International Workshop. 31-36. DOI: 10.1145/944645.944653 |
1 |
|
| 2003 |
Gai L, Gajski D. Transaction Level Modeling: An Overview Hardware/Software Codesign - Proceedings of the International Workshop. 19-24. |
1 |
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| 2003 |
Abdi S, Shin D, Gajski D. Automatic communication refinement for system level design Proceedings - Design Automation Conference. 300-305. |
1 |
|
| 2002 |
Zhu J, Gajski DD. An ultra-fast instruction set simulator Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 10: 363-373. DOI: 10.1109/Tvlsi.2002.1043339 |
1 |
|
| 2002 |
Saoud SB, Gajski DD, Gerstlauer A. Co-design of emulators for power electric processes using SpecC methodology Iecon Proceedings (Industrial Electronics Conference). 3: 2143-2148. DOI: 10.1109/IECON.2002.1185304 |
1 |
|
| 2002 |
Saoud SB, Gajski DD. Design of real-time emulators of electromechanical systems Powercon 2002 - 2002 International Conference On Power System Technology, Proceedings. 2: 828-833. DOI: 10.1109/ICPST.2002.1047515 |
0.36 |
|
| 2002 |
Cai L, Kritzinger P, Olivares M, Gajski D. Top-down system level design methodology using SpecC, VCC and SystemC Proceedings -Design, Automation and Test in Europe, Date. 1137. DOI: 10.1109/DATE.2002.998495 |
1 |
|
| 2002 |
Peng J, Abdi S, Gajski D. Automatic model refinement for fast architecture exploration [SoC design] Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference On Vlsi Design, Asp-Dac/Vlsi Design 2002. 332-337. DOI: 10.1109/ASPDAC.2002.994944 |
1 |
|
| 2002 |
Zhao S, Gajski D. Modeling a new RTL semantics in C++ Proceedings - Ieee International Symposium On Circuits and Systems. 5. |
1 |
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| 2002 |
Peng J, Gajski D. Optimal message-passing for data coherency in distributed architecture Proceedings of the International Symposium On System Synthesis. 20-25. |
1 |
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| 2002 |
Gerstlauer A, Gajski DD. System-level abstraction semantics Proceedings of the International Symposium On System Synthesis. 231-236. |
1 |
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| 2002 |
Ben Saoud S, Gajski DD, Gerstlauer A. Seamless approach for the design of control systems for power electronics and electric drives Proceedings of the Ieee International Conference On Systems, Man and Cybernetics. 6: 379-384. |
1 |
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| 2002 |
Saoud SB, Gajski DD, Dömer R. Specification and validation of new control algorithms for electric drives using SpecC language Proceedings of the Ieee International Conference On Systems, Man and Cybernetics. 5: 596-601. |
1 |
|
| 2002 |
Saoud SB, Gajski DD, Gerstlauer A. Co-design of embedded controllers for power electronics and electric systems Ieee International Symposium On Intelligent Control - Proceedings. 379-383. |
1 |
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| 2001 |
Zhu J, Gajski DD. Compiling SpecC for simulation Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2001: 57-62. DOI: 10.1109/ASPDAC.2001.913281 |
1 |
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| 2001 |
Bailey B, Gajski D. RTL semantics and methodology Proceedings of the International Symposium On System Synthesis. 69-74. |
1 |
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| 2001 |
Cai L, Gajski D, Olivarez M. Introduction of system level architecture exploration using the SpecC methodology Proceedings - Ieee International Symposium On Circuits and Systems. 5: 9-12. |
1 |
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| 2001 |
Bakshi S, Gajski DD. Performance-constrained hierarchical pipelining for behaviors, loops, and operations Acm Transactions On Design Automation of Electronic Systems. 6: 1-25. |
1 |
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| 1999 |
Zhu J, Gajski DD. OpenJ: An extensible system level design language Proceedings -Design, Automation and Test in Europe, Date. 480-484. DOI: 10.1109/DATE.1999.761169 |
1 |
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| 1999 |
Zhu J, Gajski DD. A retargetable, ultra-fast instruction set simulator Proceedings -Design, Automation and Test in Europe, Date. 298-302. DOI: 10.1109/DATE.1999.761137 |
1 |
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| 1999 |
Bakshi S, Gajski DD. Partitioning and pipelining for performance-constrained hardware/software systems Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 7: 419-432. DOI: 10.1109/92.805749 |
1 |
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| 1999 |
Zhu J, Gajski DD. Unified formal model of ISA and FSMD Hardware/Software Codesign - Proceedings of the International Workshop. 121-125. |
1 |
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| 1999 |
Zhu J, Gajski DD. Soft scheduling in high level synthesis Proceedings - Design Automation Conference. 219-224. |
1 |
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| 1998 |
Gajski DD, Vahid F, Narayan S, Gong J. SpecSyn: An environment supporting the specify-explore-refine paradigm for hardware/software system design Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 6: 84-100. DOI: 10.1109/92.661251 |
1 |
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| 1998 |
Gajski DD, Vahid F, Narayan S, Gong J. System-level exploration with SpecSyn Proceedings - Design Automation Conference. 812-817. |
1 |
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| 1997 |
Bakshi S, Gajski DD. Scheduling and pipelining algorithm for hardware/software systems Proceedings of the International Symposium On System Synthesis. 113-118. |
1 |
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| 1997 |
Bakshi S, Gajski DD. Hardware/software partitioning and pipelining Proceedings - Design Automation Conference. 713-719. |
1 |
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| 1997 |
Zhu J, Agrawal P, Gajski DD. RT level power analysis Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 517-522. |
1 |
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| 1997 |
Hong YS, Cho CH, Gajski DD. Quantitative analysis for optimizing memory allocation Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 239-245. |
1 |
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| 1996 |
Bakshi S, Gajski DD. Component selection for high-performance pipelines Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 4: 181-194. DOI: 10.1109/92.502191 |
1 |
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| 1996 |
Gajski DD. Methodology is the future Ieee Asia-Pacific Conference On Circuits and Systems - Proceedings. 269-277. |
1 |
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| 1996 |
Narayan S, Gajski DD. Rapid performance estimation for system design European Design Automation Conference - Proceedings. 206-211. |
1 |
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| 1996 |
Chang ES, Gajski DD, Narayan S. An optimal clock period selection method based on slack minimization criteria Acm Transactions On Design Automation of Electronic Systems. 1: 352-370. |
1 |
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| 1996 |
Gong J, Gajski DD, Bakshi S. Model refinement for hardware-software codesign Proceedings of European Design and Test Conference. 270-274. |
1 |
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| 1996 |
Juan HP, Gajski DD, Chaiyakul V. Clock-driven performance optimization in interactive behavioral synthesis Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 154-157. |
1 |
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| 1996 |
Bakshi S, Gajski DD, Juan HP. Component selection in resource shared and pipelined DSP applications European Design Automation Conference - Proceedings. 370-375. |
1 |
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| 1996 |
Juan HP, Gajski DD, Bakshi S. Clock optimization for high-performance pipelined design European Design Automation Conference - Proceedings. 330-335. |
1 |
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| 1995 |
Gong J, Gajski DD, Nicolau A. Performance Evaluation for Application-Specific Architectures Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 3: 483-490. DOI: 10.1109/92.475967 |
1 |
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| 1995 |
Vahid F, Gajski DD. Incremental Hardware Estimation During Hardware/Software Functional Partitioning Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 3: 459-464. DOI: 10.1109/92.407006 |
1 |
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| 1995 |
Gajski DD, Vahid F. Specification and Design of Embedded Hardware-Software Systems Ieee Design and Test of Computers. 12: 53-67. DOI: 10.1109/54.350695 |
1 |
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| 1995 |
Vahid F, Gajski DD. Clustering for improved system-level functional partitioning Proceedings of the International Symposium On System Synthesis. 28-33. |
1 |
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| 1995 |
Narayan S, Gajski DD. Interfacing incompatible protocols using interface process generation Proceedings - Design Automation Conference. 468-473. |
1 |
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| 1995 |
Vahid F, Gajski DD. Closeness metrics for system-level functional partitioning European Design Automation Conference - Proceedings. 328-333. |
1 |
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| 1995 |
Bakshi S, Gajski DD. Memory selection algorithm for high-performance pipelines European Design Automation Conference - Proceedings. 124-129. |
1 |
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| 1994 |
Gajski DD, Ramachandran L. Introduction to High-Level Synthesis Ieee Design and Test of Computers. 11: 44-54. DOI: 10.1109/54.329454 |
1 |
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| 1994 |
Holmes ND, Gajski DD. Algorithm for generation of behavioral shape functions Proceedings of the European Design and Test Conference. 314-318. |
1 |
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| 1994 |
Narayan S, Gajski DD. Synthesis of system-level bus interfaces Proceedings of the European Design and Test Conference. 395-399. |
1 |
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| 1994 |
Bakshi S, Gajski DD. Component selection algorithm for high-performance pipelines European Design Automation Conference - Proceedings. 400-405. |
1 |
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| 1994 |
Narayan S, Gajski DD. Protocol generation for communication channels Proceedings - Design Automation Conference. 547-551. |
1 |
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| 1994 |
Bakshi S, Gajski DD. Design exploration for high-performance pipelines Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 312-316. |
1 |
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| 1994 |
Vahid F, Gong J, Gajski DD. Binary-constraint search algorithm for minimizing hardware during hardware/software partitioning European Design Automation Conference - Proceedings. 214-219. |
1 |
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| 1994 |
Gong J, Gajski DD, Nicolau A. Performance evaluator for parameterized ASIC architectures European Design Automation Conference - Proceedings. 66-71. |
1 |
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| 1994 |
Ramachandran L, Gajski DD, Chaiyakul V. Algorithm for array variable clustering Proceedings of the European Design and Test Conference. 262-266. |
1 |
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| 1994 |
Vahid F, Narayan S, Gajski DD. Transformation for integrating VHDL behavioral specification with synthesis and software generation European Design Automation Conference - Proceedings. 552-557. |
1 |
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| 1994 |
Gajski DD, Vahid F, Narayan S. System-design methodology: Executable-specification refinement Proceedings of the European Design and Test Conference. 458-463. |
1 |
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| 1994 |
Juan Hp, Chaiyakul V, Gajski DD. Condition graphs for high-quality behavioral synthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 170-174. |
1 |
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| 1993 |
Rundensteiner EA, Gajski DD, Bic L. Component Synthesis From Functional Descriptions Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 12: 1287-1299. DOI: 10.1109/43.240076 |
1 |
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| 1993 |
Ramachandran L, Gajski DD. Architectural tradeoffs in synthesis of pipelined controls European Design Automation Conference - Proceedings. 244-249. |
1 |
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| 1993 |
Narayan S, Gajski DD. Features supporting sytem-level specification in HDLs European Design Automation Conference - Proceedings. 540-545. |
1 |
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| 1993 |
Chaiyakul V, Gajski DD, Ramachandran L. High-level transformations for minimizing syntactic variances Proceedings - Design Automation Conference. 413-418. |
1 |
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| 1993 |
Juan HP, Holmes ND, Bakshi S, Gajski DD. Top-down modeling of RISC processors in VHDL European Design Automation Conference - Proceedings. 454-459. |
1 |
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| 1993 |
Ramachandran L, Narayan S, Vahid F, Gajski DD. Synthesis of functions and procedures in behavioral VHDL European Design Automation Conference - Proceedings. 560-565. |
1 |
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| 1992 |
Sanjiv N, Frank V, Gajski DD. System Specification with the SpecCharts Language Ieee Design and Test of Computers. 9: 6-13. DOI: 10.1109/54.173326 |
0.36 |
|
| 1992 |
Wu ACH, Gajski DD. Partitioning Algorithms for Layout Synthesis from Register-Transfer Netlists Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 11: 453-463. DOI: 10.1109/43.125093 |
1 |
|
| 1992 |
Ramachandran L, Gajski DD. An algorithm for component selection in performance optimized scheduling 1991 Ieee International Conference On Computer-Aided Design Digest of Technical Papers. 92-95. |
1 |
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| 1992 |
Narayan S, Gajski DD. System clock estimation based on clock slack minimization European Design Automation Conference. 66-71. |
1 |
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| 1992 |
Vahid F, Gajski DD. Specification partitioning for system design Proceedings - Design Automation Conference. 219-224. |
1 |
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| 1992 |
Rundensteiner EA, Gajski DD. Functional synthesis using area and delay optimization Proceedings - Design Automation Conference. 291-296. |
1 |
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| 1992 |
Vahid F, Gajski DD. Obtaining functionally equivalent simulations using VHDL and a time-shift transformation 1991 Ieee International Conference On Computer-Aided Design Digest of Technical Papers. 362-365. |
1 |
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| 1992 |
Wu ACH, Gajski DD. Glue-logic partitioning for floorplans with a rectilinear datapath . 162-166. |
1 |
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| 1992 |
Narayan S, Vahid F, Gajski DD. System specification and synthesis with the SpecCharts language 1991 Ieee International Conference On Computer-Aided Design Digest of Technical Papers. 266-269. |
1 |
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| 1992 |
Narayan S, Vahid F, Gajski DD. Translating system specifications to VHDL . 390-394. |
1 |
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| 1992 |
Ramachandran L, Vahid F, Narayan S, Gajski DD. Semantics and synthesis of signals in behavioral VHDL European Design Automation Conference. 616-621. |
1 |
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| 1992 |
Wu ACH, Chaiyakul V, Gajski DD. Layout-area models for high-level synthesis 1991 Ieee International Conference On Computer-Aided Design Digest of Technical Papers. 34-37. |
1 |
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| 1992 |
Chaiyakul V, Wu ACH, Gajski DD. Timing models for high-level synthesis European Design Automation Conference. 60-65. |
1 |
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| 1992 |
Wu ACH, Hadley TS, Gajski DD. Efficient multi-view design model for real-time interactive synthesis Ieee/Acm International Conference On Computer-Aided Design. 328-331. |
1 |
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| 1990 |
Wu MY, Gajski DD. Hypertool: A Programming Aid for Message-Passing Systems Ieee Transactions On Parallel and Distributed Systems. 1: 330-343. DOI: 10.1109/71.80160 |
1 |
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| 1990 |
Dutt ND, Gajski DD. Design synthesis and silicon compilation Ieee Design and Test of Computers. 7: 8-23. DOI: 10.1109/54.64954 |
1 |
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| 1990 |
Brewer F, Gajski D. Chippe: A System for Constraint Driven Behavioral Synthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 9: 681-695. DOI: 10.1109/43.55208 |
1 |
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| 1990 |
Chen GD, Gajski DD. An intelligent component database for behavioral synthesis 27th Acm/Ieee Design Automation Conference. Proceedings 1990. 150-155. |
1 |
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| 1990 |
Dutt N, Hadley T, Gajski DD. An intermediate representation for behavioral synthesis 27th Acm/Ieee Design Automation Conference. Proceedings 1990. 14-19. |
1 |
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| 1990 |
Rundensteiner EA, Gajski DD, Bic L. The component synthesis algorithm: Technology mapping for register transfer descriptions 1990 Ieee International Conference On Computer-Aided Design. Digest of Technical Papers. 208-211. |
1 |
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| 1989 |
Wu MY, Gajski DD. Computer-Aided Programming for Message-Passing Systems: Problems and a Solution Proceedings of the Ieee. 77: 1983-1991. DOI: 10.1109/5.48836 |
1 |
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| 1989 |
Lursinsap C, Gajski D. Power routing in channelless floorplan layouts Integration, the Vlsi Journal. 8: 249-268. DOI: 10.1016/0167-9260(89)90019-9 |
1 |
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| 1989 |
Dutt ND, Gajski DD. Designer controlled behavioral synthesis Proceedings - Design Automation Conference. 754-757. |
1 |
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| 1989 |
Kipps JR, Gajski DD. Role of learning in logic synthesis . 252-258. |
1 |
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| 1989 |
Lis JS, Gajski DD. VHDL synthesis using structured modeling Proceedings - Design Automation Conference. 606-609. |
1 |
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| 1989 |
Wu MY, Gajski DD. Hypertool: A programming aid for multicomputers Proceedings of the International Conference On Parallel Processing. 2: 15-18. |
1 |
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| 1988 |
Lursinsap C, Gajski DD. A Technique for Pull-Up Transistor Folding Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 7: 887-896. DOI: 10.1109/43.3220 |
1 |
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| 1988 |
Lin YL, Gajski DD. LES: A Layout Expert System Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 7: 868-876. DOI: 10.1109/43.3218 |
1 |
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| 1988 |
Wu MY, Gajski DD. A programming aid for hypercube architectures The Journal of Supercomputing. 2: 349-372. DOI: 10.1007/Bf00129784 |
1 |
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| 1988 |
Lis JS, Gajski DD. Synthesis from VHDL . 378-381. |
1 |
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| 1987 |
Pangrle BM, Gajski DD. Design Tools for Intelligent Silicon Compilation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 6: 1098-1112. DOI: 10.1109/TCAD.1987.1270350 |
0.36 |
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| 1987 |
Pangrle BM, Gajski DD. SLICER: A STATE SYNTHESIZER FOR INTELLIGENT SILICON COMPILATION . 42-45. |
1 |
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| 1987 |
Lin YLS, Gajski DD, Tago H. FLEXIBLE-CELL APPROACH FOR MODULE GENERATION Proceedings of the Custom Integrated Circuits Conference. 9-12. |
1 |
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| 1986 |
Bilgory A, Gajski DD. A heuristic for suffix solutions Ieee Transactions On Computers. 34-42. DOI: 10.1109/TC.1986.1676655 |
1 |
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| 1986 |
Peir JK, Gajski DD. TOWARD COMPUTER-AIDED PROGRAMMING FOR MULTIPROCESSORS . 191-202. |
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| 1986 |
Peir JK, Gajski DD. CAMP: A PROGRAMMING AIDE FOR MULTIPROCESSORS Proceedings of the International Conference On Parallel Processing. 475-482. |
1 |
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| 1986 |
Pangrle BM, Gajski DD. STATE SYNTHESIS AND CONNECTIVITY BINDING FOR MICROARCHITECTURE COMPILATION . 210-213. |
1 |
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| 1986 |
Gajski DD, Dutt ND, Pangrle BM. SILICON COMPILATION (TUTORIAL) Proceedings of the Custom Integrated Circuits Conference. 102-110. |
1 |
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| 1985 |
Gajski DD, Peir JK. Essential Issues in Multiprocessor Systems Computer. 18: 9-27. DOI: 10.1109/MC.1985.1662920 |
1 |
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| 1985 |
Gajski DD, Peir JK. Comparison of five multiprocessor systems Parallel Computing. 2: 265-282. DOI: 10.1016/0167-8191(85)90008-0 |
1 |
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| 1985 |
Gajski DD. DOES GENERAL PURPOSE MEAN GOOD FOR NOTHING? Algorithmically Spec Parallel Comput. 249-250. |
1 |
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| 1985 |
Gajski DD. ARSENIC SILICON COMPILER Proceedings - Ieee International Symposium On Circuits and Systems. 399-402. |
1 |
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| 1985 |
Healey ST, Gajski DD. DECOMPOSITION OF LOGIC NETWORKS INTO SILICON Proceedings - Design Automation Conference. 162-168. |
1 |
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| 1985 |
Peir JK, Gajski DD. DATA FLOW EXECUTION OF FORTRAN LOOPS . 129-138. |
1 |
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| 1984 |
Kim W, Gajski D, Kuck DJ. A parallel pipelined relational query processor Acm Transactions On Database Systems (Tods). 9: 214-235. DOI: 10.1145/329.332 |
1 |
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| 1984 |
Banerjee U, Gajski DD. Fast Execution of Loops with if Statements Ieee Transactions On Computers. 1030-1033. DOI: 10.1109/TC.1984.1676377 |
1 |
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| 1984 |
Gajski DD. SILICON COMPILERS AND EXPERT SYSTEMS FOR VLSI Proceedings - Design Automation Conference. 86-87. |
1 |
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| 1984 |
Abraham S, Gajski DD. COMMUNICATION ALGORITHM FOR A WAFER SCALE INTEGRATED MULTIPROCESSOR Proceedings of the International Conference On Parallel Processing. 147-154. |
1 |
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| 1984 |
Healey ST, Persels SD, Gajski DD. IBL - A LANGUAGE FOR ABSTRACT AND GEOMETRIC VLSI LAYOUT . 55-60. |
1 |
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| 1984 |
Raj VK, Pangrle BM, Gajski DD. MICROPROCESSOR SYNTHESIS Proceedings - Design Automation Conference. 676-678. |
1 |
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| 1983 |
Banerjee U, Gajski D, Kuck D. ACCESSING SPARE ARRAYS IN PARALLEL MEMORIES Journal of Vlsi and Computer Systems. 1: 69-100. |
1 |
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| 1982 |
Gajski DD, Padua DA, Kuck DJ, Kuhn RH. A Second Opinion on Data Flow Machines and Languages Computer. 15: 58-69. DOI: 10.1109/MC.1982.1653942 |
1 |
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| 1982 |
Gajski DD. STRUCTURE OF A SILICON COMPILER Proceedings - Ieee International Conference On Circuits and Computers. 272-276. |
1 |
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| 1982 |
Bilgory A, Gajski DD. AUTOMATIC GENERATION OF CELLS FOR RECURRENCE STRUCTURES Proceedings - Design Automation Conference. 306-313. |
1 |
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| 1981 |
Abraham JA, Gajski DD. Design of Testable Structures Defined by Simple Loops Ieee Transactions On Circuits and Systems. 28: 1079-1088. DOI: 10.1109/TCS.1981.1084931 |
1 |
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| 1981 |
Gajski DD. An Algorithm for Solving Linear Recurrence Systems on Parallel and Pipelined Machines Ieee Transactions On Computers. 190-206. DOI: 10.1109/TC.1981.1675755 |
1 |
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| 1981 |
Bilgory A, Gajski DD. ALGORITHM FOR EFFICIENT LAYOUTS OF PARALLES SUFFIX SOLUTIONS Proceedings of the International Conference On Parallel Processing. 245-252. |
1 |
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| 1981 |
Gajski DD, Kuck DJ, Padua DA. DEPENDENCE DRIVEN COMPUTATION Digest of Papers - Ieee Computer Society International Conference. 168-172. |
1 |
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| 1981 |
Casavant AE, Gajski DD, Kuck DJ. AUTOMATIC DESIGN WITH DEPENDENCE GRAPHS Jahrbuch Der Schiffbautechnischen Gesellschaft. 506-515. |
1 |
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| 1980 |
Gajski DD. Parallel Compressors Ieee Transactions On Computers. 393-398. DOI: 10.1109/TC.1980.1675589 |
1 |
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| 1980 |
Banerjee U, Gajski D, Kuck D. ARRAY MACHINE CONTROL UNITS FOR LOOPS CONTAINING IFs Proceedings of the International Conference On Parallel Processing. 28-36. |
1 |
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| 1979 |
Gajski DD. SOLVING BANDED TRIANGULAR SYSTEMS ON PIPELINED MACHINES Assembly Engineering. 308-319. |
1 |
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| 1979 |
Gajski DD. PROCESSOR ARRAY FOR COMPUTING LINEAR RECURRENCE SYSTEMS . 246-256. |
1 |
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| 1979 |
Gajski DD, Rubinfield LP. DESIGN OF ARITHMETIC ELEMENTS FOR BURROUGHS SCIENTIFIC PROCESSOR . 245-256. |
1 |
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| 1978 |
Gajski DD, Tulpule BR. HIGH-SPEED MASKING ROTATOR Digital Processes. 4: 67-81. |
1 |
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| 1977 |
Gajski DD. GSI IMPACT: LOGIC-DESIGN POINT OF VIEW . 312-326. |
1 |
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| 1977 |
Gajski DD, Vora C. HIGH-SPEED MODULO-3 GENERATOR Electronics Letters. 13: 770-772. |
1 |
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| 1975 |
Gajski DD. ARRAYS FOR GENERATING ARBITRARY MASK VECTORS Electronics Letters. 11: 442-443. |
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