Azad Naeemi, Ph.D. - Publications

Affiliations: 
2003 Georgia Institute of Technology, Atlanta, GA 
Area:
Microelectronics/Microsystems

130 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2016 Pan C, Naeemi A. A proposal for energy-efficient cellular neural network based on spintronic devices Ieee Transactions On Nanotechnology. 15: 820-827. DOI: 10.1109/Tnano.2016.2598147  1
2016 Aghasi H, Iraei RM, Naeemi A, Afshari E. Smart detector cell: A scalable all-spin circuit for low power non-boolean pattern recognition Ieee Transactions On Nanotechnology. 15: 356-366. DOI: 10.1109/Tnano.2016.2530779  1
2016 Kani N, Chang SC, Dutta S, Naeemi A. A Model Study of an Error-Free Magnetization Reversal Through Dipolar Coupling in a Two-Magnet System Ieee Transactions On Magnetics. 52. DOI: 10.1109/Tmag.2015.2475426  1
2016 Kumar V, Oh H, Zhang X, Zheng L, Bakir MS, Naeemi A. Impact of On-Chip Interconnect on the Performance of 3-D Integrated Circuits With Through Silicon Vias: Part I Ieee Transactions On Electron Devices. DOI: 10.1109/Ted.2016.2556693  1
2016 Zhang X, Kumar V, Oh H, Zheng L, May GS, Naeemi A, Bakir MS. Impact of On-Chip Interconnect on the Performance of 3-D Integrated Circuits with Through-Silicon Vias: Part II Ieee Transactions On Electron Devices. 63: 2510-2516. DOI: 10.1109/TED.2016.2556693  1
2016 Pan C, Naeemi A. Interconnect design and benchmarking for charge-based beyond-CMOS device proposals Ieee Electron Device Letters. 37: 508-511. DOI: 10.1109/Led.2016.2532350  1
2016 Naeemi A, Sou-Chi C, Dutta S, Chenyun P, Manipatruni S, Nikonov D, Young I. Spin-based interconnect technology and design 2016 Ieee International Interconnect Technology Conference / Advanced Metallization Conference, Iitc/Amc 2016. DOI: 10.1109/IITC-AMC.2016.7507735  1
2016 Pan C, Chang SC, Naeemi A. Performance analyses and benchmarking for spintronic devices and interconnects 2016 Ieee International Interconnect Technology Conference / Advanced Metallization Conference, Iitc/Amc 2016. 56-58. DOI: 10.1109/IITC-AMC.2016.7507679  1
2015 Dutta S, Chang SC, Kani N, Nikonov DE, Manipatruni S, Young IA, Naeemi A. Non-volatile Clocked Spin Wave Interconnect for Beyond-CMOS Nanomagnet Pipelines. Scientific Reports. 5: 9861. PMID 25955353 DOI: 10.1038/Srep09861  1
2015 Chang SC, Ceyhan A, Kumar V, Naeemi A. Performance modeling for emerging interconnect technologies in CMOS and beyond-CMOS circuits Proceedings of the International Symposium On Low Power Electronics and Design. 2015: 63-68. DOI: 10.1145/2627369.2631638  1
2015 Prasad D, Ceyhan A, Pan C, Naeemi A. Adapting Interconnect Technology to Multigate Transistors for Optimum Performance Ieee Transactions On Electron Devices. 62: 3938-3944. DOI: 10.1109/Ted.2015.2487888  1
2015 Dutta S, Nikonov DE, Manipatruni S, Young IA, Naeemi A. Compact Physical Model for Crosstalk in Spin-Wave Interconnects Ieee Transactions On Electron Devices. 62: 3863-3869. DOI: 10.1109/Ted.2015.2478842  1
2015 Pan C, Raghavan P, Yakimets D, Debacker P, Catthoor F, Collaert N, Tokei Z, Verkest D, Thean AVY, Naeemi A. Technology/System Codesign and Benchmarking for Lateral and Vertical GAA Nanowire FETs at 5-nm Technology Node Ieee Transactions On Electron Devices. DOI: 10.1109/Ted.2015.2461457  1
2015 Pan C, Baert R, Ciofi I, Tokei Z, Naeemi A. System-Level Variation Analysis for Interconnection Networks at Sub-10-nm Technology Nodes Using Multiple Patterning Techniques Ieee Transactions On Electron Devices. 62: 2071-2077. DOI: 10.1109/Ted.2015.2427033  1
2015 Pan C, Raghavan P, Ceyhan A, Catthoor F, Tokei Z, Naeemi A. Technology/circuit/system co-optimization and benchmarking for multilayer graphene interconnects at sub-10-nm technology node Ieee Transactions On Electron Devices. 62: 1530-1536. DOI: 10.1109/Ted.2015.2409875  1
2015 Ceyhan A, Jung M, Panth S, Lim SK, Naeemi A. Evaluating Chip-Level Impact of Cu/Low-κ Performance Degradation on Circuit Performance at Future Technology Nodes Ieee Transactions On Electron Devices. DOI: 10.1109/Ted.2015.2394407  1
2015 Pan C, Naeemi A. A paradigm shift in local interconnect technology design in the era of nanoscale multigate and gate-all-around devices Ieee Electron Device Letters. 36: 274-276. DOI: 10.1109/Led.2015.2394366  1
2015 Chang SC, Dutta S, Manipatruni S, Nikonov DE, Young IA, Naeemi A. Interconnects for All-Spin Logic Using Automotion of Domain Walls Ieee Journal On Exploratory Solid-State Computational Devices and Circuits. 1: 49-57. DOI: 10.1109/Jxcdc.2015.2448415  1
2015 Pan C, Naeemi A. A fast system-level design methodology for heterogeneous multi-core processors using emerging technologies Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 5: 75-87. DOI: 10.1109/Jetcas.2015.2398218  1
2015 Pan C, Raghavan P, Catthoor F, Tokei Z, Naeemi A. Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology node Proceedings - International Symposium On Quality Electronic Design, Isqed. 2015: 599-603. DOI: 10.1109/ISQED.2015.7085495  1
2015 Peng R, Dorn B, Naeemi A, Jafarinaimi N. Interactive visualizations for teaching quantum mechanics and semiconductor physics Proceedings - Frontiers in Education Conference, Fie. 2015. DOI: 10.1109/FIE.2014.7044207  1
2015 Mohseni J, Pan C, Naeemi A. Performace modeling and optimization for on-chip interconnects in memory arrays 2015 Ieee 24th Conference On Electrical Performance of Electronic Packaging and Systems, Epeps 2015. 149-152. DOI: 10.1109/EPEPS.2015.7347150  1
2015 Pan C, Mukhopadhyay S, Naeemi A. System-level chip/package co-design for multi-core processors implemented with power-gating technique 2014 Ieee 23rd Conference On Electrical Performance of Electronic Packaging and Systems, Epeps 2014. 11-14. DOI: 10.1109/EPEPS.2014.7103580  1
2015 Kani N, Dutta S, Naeemi A. Analysis of coupling strength in multi-domain magneto-systems Device Research Conference - Conference Digest, Drc. 2015: 111-112. DOI: 10.1109/DRC.2015.7175580  1
2015 Dutta S, Nikonov DE, Manipatruni S, Young IA, Naeemi A. Phase-dependent deterministic switching of magnetoelectric spin wave detector in the presence of thermal noise via compensation of demagnetization Applied Physics Letters. 107. DOI: 10.1063/1.4935690  1
2015 Rakheja S, Ceyhan A, Naeemi A. Interconnect considerations: Interconnect considerations Cmos and Beyond: Logic Switches For Terascale Integrated Circuits. 381-412. DOI: 10.1017/CBO9781107337886.021  1
2014 Naeemi A, Pan C, Ceyhan A, Iraei RM, Kumar V, Rakheja S. Beol scaling limits and next generation technology prospects Proceedings - Design Automation Conference. DOI: 10.1145/2593069.2596672  1
2014 Chang SC, Manipatruni S, Nikonov DE, Young IA, Naeemi A. Design and analysis of Si interconnects for all-spin logic Ieee Transactions On Magnetics. 50. DOI: 10.1109/Tmag.2014.2325536  1
2014 Dutta S, Nikonov DE, Manipatruni S, Young IA, Naeemi A. SPICE circuit modeling of PMA spin wave bus excited using magnetoelectric effect Ieee Transactions On Magnetics. 50. DOI: 10.1109/Tmag.2014.2320942  1
2014 Chang SC, Iraei RM, Manipatruni S, Nikonov DE, Young IA, Naeemi A. Design and analysis of copper and aluminum interconnects for all-spin logic Ieee Transactions On Electron Devices. 61: 2905-2911. DOI: 10.1109/Ted.2014.2327057  1
2014 Bonhomme P, Manipatruni S, Iraei RM, Rakheja S, Chang SC, Nikonov DE, Young IA, Naeemi A. Circuit simulation of magnetization dynamics and spin transport Ieee Transactions On Electron Devices. 61: 1553-1560. DOI: 10.1109/Ted.2014.2305987  1
2014 Kumar V, Sharma R, Uzunlar E, Zheng L, Bashirullah R, Kohl P, Bakir MS, Naeemi A. Airgap interconnects: Modeling, optimization, and benchmarking for backplane, PCB, and interposer applications Ieee Transactions On Components, Packaging and Manufacturing Technology. 4: 1335-1346. DOI: 10.1109/Tcpmt.2014.2326798  1
2014 Kani N, Naeemi A. Wiring resource minimization for physically-complex Network-on-Chip architectures International System On Chip Conference. 261-266. DOI: 10.1109/SOCC.2014.6948938  1
2014 Kani N, Naeemi A. Pipeline design in spintronic circuits Proceedings of the 2014 Ieee/Acm International Symposium On Nanoscale Architectures, Nanoarch 2014. 110-115. DOI: 10.1109/NANOARCH.2014.6880496  1
2014 Pan C, Naeemi A. A proposal for a novel hybrid interconnect technology for the end of roadmap Ieee Electron Device Letters. 35: 250-252. DOI: 10.1109/Led.2013.2291783  1
2014 Pan C, Mukhopadhyay S, Naeemi A. An analytical approach to system-level variation analysis and optimization for multi-core processor Proceedings - International Symposium On Quality Electronic Design, Isqed. 99-106. DOI: 10.1109/ISQED.2014.6783312  1
2014 Kumar V, Nashed R, Brenner K, Sandhu R, Naeemi A. System level analysis and benchmarking of graphene interconnects for low-power applications Ieee International Symposium On Electromagnetic Compatibility. 2014: 192-197. DOI: 10.1109/ISEMC.2014.6898968  1
2014 Iraei RM, Bonhomme P, Kani N, Manipatruni S, Nikonov DE, Young IA, Naeemi A. Impact of dimensional scaling and size effects on beyond CMOS All-Spin Logic interconnects 2014 Ieee International Interconnect Technology Conference / Advanced Metallization Conference, Iitc/Amc 2014. 353-356. DOI: 10.1109/IITC.2014.6831833  1
2014 Ceyhan A, Jung M, Panth S, Lim SK, Naeemi A. Impact of size effects in local interconnects for future technology nodes: A study based on full-chip layouts 2014 Ieee International Interconnect Technology Conference / Advanced Metallization Conference, Iitc/Amc 2014. 345-348. DOI: 10.1109/IITC.2014.6831831  1
2014 Naeemi A. SPICE models for metallic all-spin-logic devices and interconnects Device Research Conference - Conference Digest, Drc. 287-288. DOI: 10.1109/DRC.2014.6872409  1
2013 Rakheja S, Naeemi A. Roles of doping, temperature, and electric field on spin transport through semiconducting channels in spin valves Ieee Transactions On Nanotechnology. 12: 796-805. DOI: 10.1109/Tnano.2013.2274494  1
2013 Ceyhan A, Naeemi A. Cu/Low-k interconnect technology design and benchmarking for future technology nodes Ieee Transactions On Electron Devices. 60: 4041-4047. DOI: 10.1109/Ted.2013.2286176  1
2013 Rakheja S, Chang SC, Naeemi A. Impact of dimensional scaling and size effects on spin transport in copper and aluminum interconnects Ieee Transactions On Electron Devices. 60: 3913-3919. DOI: 10.1109/Ted.2013.2282615  1
2013 Ceyhan A, Naeemi A. Cu interconnect limitations and opportunities for SWNT interconnects at the end of the roadmap Ieee Transactions On Electron Devices. 60: 374-382. DOI: 10.1109/Ted.2012.2224663  1
2013 Rakheja S, Kumar V, Naeemi A. Performance modeling for interconnects for conventional and emerging switches International Workshop On System Level Interconnect Prediction, Slip. DOI: 10.1109/SLIP.2013.6681683  1
2013 Rakheja S, Naeemi A. Communicating novel computational state variables: Post-CMOS logic Ieee Nanotechnology Magazine. 7: 15-23. DOI: 10.1109/Mnano.2012.2237314  1
2013 Zheng P, Bryan SE, Yang Y, Murali R, Naeemi A, Meindl JD. Hydrogenation of graphene nanoribbon edges: Improvement in carrier transport Ieee Electron Device Letters. 34: 707-709. DOI: 10.1109/Led.2013.2253593  1
2013 Rakheja S, Kumar V, Naeemi A. Evaluation of the potential performance of graphene nanoribbons as on-chip interconnects Proceedings of the Ieee. 101: 1740-1765. DOI: 10.1109/JPROC.2013.2260235  1
2013 Ceyhan A, Naeemi A. Impact of conventional and emerging interconnects on the circuit performance of various post-CMOS devices Proceedings - International Symposium On Quality Electronic Design, Isqed. 203-209. DOI: 10.1109/ISQED.2013.6523611  1
2013 Pan C, Ceyhan A, Naeemi A. System-level optimization and benchmarking for InAs nanowire based gate-all-around tunneling FETs Proceedings - International Symposium On Quality Electronic Design, Isqed. 196-202. DOI: 10.1109/ISQED.2013.6523610  1
2013 Kumar V, Rakheja S, Naeemi A. Review of multi-layer graphene nanoribbons for on-chip interconnect applications Ieee International Symposium On Electromagnetic Compatibility. 528-533. DOI: 10.1109/ISEMC.2013.6670470  1
2013 Pan C, Naeemi A. System-level analysis for 3D interconnection networks Proceedings of the 2013 Ieee International Interconnect Technology Conference, Iitc 2013. DOI: 10.1109/IITC.2013.6615597  1
2013 Kumar V, Zheng L, Bakir M, Naeemi A. Compact modeling and optimization of fine-pitch interconnects for silicon interposers Proceedings of the 2013 Ieee International Interconnect Technology Conference, Iitc 2013. DOI: 10.1109/IITC.2013.6615571  1
2013 Uzunlar E, Sharma R, Saha R, Kumar V, Bashirullah R, Naeemi A, Kohl PA. Design and fabrication of ultra low-loss, high-performance 3D chip-chip air-clad interconnect pathway Proceedings - Electronic Components and Technology Conference. 1425-1432. DOI: 10.1109/ECTC.2013.6575760  1
2013 Rakheja S, Naeemi A. Transport of novel state variables Graphene Nanoelectronics: From Materials to Circuits. 113-136. DOI: 10.1007/978-1-4614-0548-1_5  1
2012 D'amore M, Sarto MS, Hanson GW, Naeemi A, Tay BK. Guest Editorial Special Issue on applications of nanotechnology in electromagnetic compatibility (nano-EMC) Ieee Transactions On Electromagnetic Compatibility. 54: 2-5. DOI: 10.1109/TEMC.2012.2185501  1
2012 Kumar V, Rakheja S, Naeemi A. Performance and energy-per-bit modeling of multilayer graphene nanoribbon conductors Ieee Transactions On Electron Devices. 59: 2753-2761. DOI: 10.1109/Ted.2012.2208753  1
2012 Rakheja S, Naeemi A. Graphene nanoribbon spin interconnects for nonlocal spin-torque circuits: Comparison of performance and energy per bit with CMOS interconnects Ieee Transactions On Electron Devices. 59: 51-59. DOI: 10.1109/Ted.2011.2171186  1
2012 Huang G, Bakir MS, Naeemi A, Meindl JD. Power delivery for 3-D chip stacks: Physical modeling and design implication Ieee Transactions On Components, Packaging and Manufacturing Technology. 2: 852-859. DOI: 10.1109/Tcpmt.2012.2185047  1
2012 Rakheja S, Naeemi A. Compact modeling of spin-transport parameters in semiconducting channels in non-local spin-torque devices Proceedings of the Ieee Conference On Nanotechnology. DOI: 10.1109/NANO.2012.6321912  1
2012 Pan C, Naeemi A. Device- and system-level performance modeling for graphene P-N junction logic Proceedings - International Symposium On Quality Electronic Design, Isqed. 262-269. DOI: 10.1109/ISQED.2012.6187504  1
2012 Kumar V, Naeemi A. Analytical models for the frequency response of multi-layer graphene nanoribbon interconnects Ieee International Symposium On Electromagnetic Compatibility. 440-445. DOI: 10.1109/ISEMC.2012.6351837  1
2012 Kumar V, Sharma R, Chen J, Kapoor A, Bashirullah R, Kohl P, Naeemi A. Compact modeling and performance optimization of 3D chip-to-chip interconnects with transmission lines, vias and discontinuities 2012 Ieee International Interconnect Technology Conference, Iitc 2012. DOI: 10.1109/IITC.2012.6251646  1
2012 Kani N, Naeemi A. Circuit-technology co-optimization of heterogeneous hierarchical network-on-chips 2012 Ieee International Interconnect Technology Conference, Iitc 2012. DOI: 10.1109/IITC.2012.6251645  1
2012 Ceyhan A, Naeemi A. System-level design and performance modeling for multilevel interconnect networks for carbon nanotube field-effect transistors Icicdt 2012 - Ieee International Conference On Integrated Circuit Design and Technology. DOI: 10.1109/ICICDT.2012.6232851  1
2012 Pan C, Naeemi A. System-level optimization and benchmarking of graphene PN junction logic system based on empirical CPI model Icicdt 2012 - Ieee International Conference On Integrated Circuit Design and Technology. DOI: 10.1109/ICICDT.2012.6232850  1
2012 Pan C, Naeemi A. System-level performance optimization and benchmarking for on-chip graphene interconnects 2012 Ieee 21st Conference On Electrical Performance of Electronic Packaging and Systems, Epeps 2012. 33-36. DOI: 10.1109/EPEPS.2012.6457837  1
2012 Sharma R, Uzunlar E, Kumar V, Saha R, Yeow X, Bashirullah R, Naeemi A, Kohl P. Design and fabrication of low-loss horizontal and vertical interconnect links using air-clad transmission lines and through silicon vias Proceedings - Electronic Components and Technology Conference. 2005-2012. DOI: 10.1109/ECTC.2012.6249115  1
2011 Jamal O, Naeemi A. Ultralow-power single-wall carbon nanotube interconnects for subthreshold circuits Ieee Transactions On Nanotechnology. 10: 99-101. DOI: 10.1109/Tnano.2010.2095428  1
2011 Balakrishnan A, Naeemi A. Interconnect network analysis of many-core chips Ieee Transactions On Electron Devices. 58: 2831-2837. DOI: 10.1109/Ted.2011.2158104  1
2011 Rakheja S, Naeemi A. Modeling interconnects for post-CMOS devices and comparison with copper interconnects Ieee Transactions On Electron Devices. 58: 1319-1328. DOI: 10.1109/Ted.2011.2109004  1
2011 Rakheja S, Naeemi A. On physical limits and challenges of interconnects for spin devices Proceedings of the Ieee Conference On Nanotechnology. 1389-1394. DOI: 10.1109/NANO.2011.6144321  1
2011 Rakheja S, Naeemi A. Interconnection aspects of spin torque devices: Delay, energy-per-bit, and circuit size modeling Proceedings of the 12th International Symposium On Quality Electronic Design, Isqed 2011. 736-744. DOI: 10.1109/ISQED.2011.5770811  1
2011 Kumar V, Rakheja S, Naeemi A. Modeling and optimization for multi-layer graphene nanoribbon conductors 2011 Ieee International Interconnect Technology Conference and 2011 Materials For Advanced Metallization, Iitc/Mam 2011. DOI: 10.1109/IITC.2011.5940340  1
2011 Ceyhan A, Naeemi A. Multilevel interconnect networks for the end of the roadmap: Conventional Cu/low-k and emerging carbon based interconnects 2011 Ieee International Interconnect Technology Conference and 2011 Materials For Advanced Metallization, Iitc/Mam 2011. DOI: 10.1109/IITC.2011.5940314  1
2011 Rakheja S, Naeemi A. Interconnect performance and energy-per-bit for post-CMOS logic circuits: Modeling, analysis, and comparison with CMOS logic 2011 Ieee International Interconnect Technology Conference and 2011 Materials For Advanced Metallization, Iitc/Mam 2011. DOI: 10.1109/IITC.2011.5940267  1
2011 Banerjee A, Chatterjee S, Naeemi A, Chatterjee A. Power aware post-manufacture tuning of analog nanocircuits Proceedings - 16th Ieee European Test Symposium, Ets 2011. 57-62. DOI: 10.1109/ETS.2011.48  1
2011 Kumar V, Bashirullah R, Naeemi A. Modeling, optimization and benchmarking of chip-to-chip electrical interconnects with low loss air-clad dielectrics Proceedings - Electronic Components and Technology Conference. 2084-2090. DOI: 10.1109/ECTC.2011.5898805  1
2010 Rakheja S, Naeemi A. Interconnects for novel state variables: Performance modeling and device and circuit implications Ieee Transactions On Electron Devices. 57: 2711-2718. DOI: 10.1109/Ted.2010.2062186  1
2010 Balakrishnan A, Naeemi A. Optimal global interconnects for networks-on-chip in many-core architectures Ieee Electron Device Letters. 31: 290-292. DOI: 10.1109/Led.2010.2041319  1
2010 Meindl J, Naeemi A, Bakir M, Murali R. Nanoelectronics in retrospect, prospect and principle Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 53: 31-35. DOI: 10.1109/ISSCC.2010.5434062  1
2010 Jamal O, Naeemi A. Evolutionary and revolutionary interconnect technologies for performance enhancement of subthreshold circuits 2010 Ieee International Interconnect Technology Conference, Iitc 2010. DOI: 10.1109/IITC.2010.5510733  1
2010 Rakheja S, Naeemi A, Meindl JD. Physical limitations on delay and energy dissipation of interconnects for post-CMOS devices 2010 Ieee International Interconnect Technology Conference, Iitc 2010. DOI: 10.1109/IITC.2010.5510448  1
2010 Balakrishnan A, Naeemi A. Bandwidth, delay and energy aware optimization of global interconnects for many-core architectures 2010 Ieee International Interconnect Technology Conference, Iitc 2010. DOI: 10.1109/IITC.2010.5510317  1
2010 Naeemi A. Work in progress - Carbon nanomaterials: A platform to teach fundamentals of nanoelectronics Proceedings - Frontiers in Education Conference, Fie. S3C1-S3C2. DOI: 10.1109/FIE.2010.5673499  1
2009 Naeemi A, Meindl JD. Carbon nanotube interconnects Annual Review of Materials Research. 39: 255-275. DOI: 10.1146/Annurev-Matsci-082908-145247  1
2009 Naeemi A, Meindl JD. Compact physics-based circuit models for graphene nanoribbon interconnects Ieee Transactions On Electron Devices. 56: 1822-1833. DOI: 10.1109/Ted.2009.2026122  1
2008 Naeemi A, Meindl JD. Performance modeling for single- and multiwall carbon nanotubes as signal and power interconnects in gigascale systems Ieee Transactions On Electron Devices. 55: 2574-2582. DOI: 10.1109/Ted.2008.2003028  1
2008 Naeemi A, Meindl JD. Electron transport modeling for junctions of zigzag and armchair graphene nanoribbons (GNRs) Ieee Electron Device Letters. 29: 497-499. DOI: 10.1109/Led.2008.920278  1
2008 Naeemi A, Meindl JD. Performance benchmarking for graphene nanoribbon, carbon Nanotube, and Cu interconnects 2008 Ieee International Interconnect Technology Conference, Iitc. 183-185. DOI: 10.1109/IITC.2008.4546961  1
2008 Naeemi A, Meindl JD. Physical models for electron transport in graphene nanoribbons and their junctions Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 400-405. DOI: 10.1109/ICCAD.2008.4681605  1
2008 Huang G, Naeemi A, Zhou T, O'Connor D, Muszynski A, Singh B, Becker D, Venuto J, Meindl JD. Compact physical models for chip and package power and ground distribution networks for gigascale integration (GSI) Proceedings - Electronic Components and Technology Conference. 646-651. DOI: 10.1109/ECTC.2008.4550040  1
2008 Bakir MS, King C, Sekar D, Thacker H, Dang B, Huang G, Naeemi A, Meindl JD. 3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation Proceedings of the Custom Integrated Circuits Conference. 663-670. DOI: 10.1109/CICC.2008.4672173  1
2008 Huang G, Sekar D, Naeemi A, Shakeri K, Meindl JD. Physical model for power supply noise and chip/package co-design in gigascale systems with the consideration of hot spots Proceedings of the Custom Integrated Circuits Conference. 841-844. DOI: 10.1109/CICC.2007.4405859  1
2008 Ni D, Lam T, Le Coz YL, Naeemi A, Meindl JD. Estimation of an RLC granularity metric for a CNT-bundle interconnect stack 2008 Proceedings - 25th International Vlsi Multilevel Interconnection Conference, Vmic 2008. 291-295.  1
2007 Naeemi A, Meindl JD. Design and performance modeling for single-walled carbon nanotubes as local, semiglobal, and global interconnects in gigascale integrated systems Ieee Transactions On Electron Devices. 54: 26-37. DOI: 10.1109/Ted.2006.887210  1
2007 Naeemi A, Bakir MS. Chip-level and input/output interconnects for gigascale SOCs: Limits and opportunities 2006 Ieee International Systems-On-Chip Conference, Soc. 323-324. DOI: 10.1109/SOCC.2006.283908  1
2007 Naeemi A, Meindl JD. Conductance modeling for graphene nanoribbon (GNR) interconnects Ieee Electron Device Letters. 28: 428-431. DOI: 10.1109/Led.2007.895452  1
2007 Naeemi A, Meindl JD. Physical modeling of temperature coefficient of resistance for single- and multi-wall carbon nanotube interconnects Ieee Electron Device Letters. 28: 135-138. DOI: 10.1109/Led.2006.889240  1
2007 Sekar DC, Naeemi A, Sarvari R, Davis JA, Meindl JD. IntSim: A CAD tool for optimization of multilevel interconnect networks Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 560-567. DOI: 10.1109/ICCAD.2007.4397324  1
2007 Huang G, Bakir M, Naeemi A, Chen H, Meindl JD. Power delivery for 3D chip stacks: Physical modeling and design implication Ieee Topical Meeting On Electrical Performance of Electronic Packaging. 205-208. DOI: 10.1109/EPEP.2007.4387161  1
2007 Gang H, Sekar DC, Naeemi A, Shakeri K, Meindl JD. Compact physical models for power supply noise and chip/package co-design of gigascale integration Proceedings - Electronic Components and Technology Conference. 1659-1666. DOI: 10.1109/ECTC.2007.374017  1
2007 Naeemi A, Huang G, Meindl JD. Performance modeling for carbon nanotube interconnects in on-chip power distribution Proceedings - Electronic Components and Technology Conference. 420-428. DOI: 10.1109/ECTC.2007.373831  1
2007 Naeemi A, Sarvari R, Meindl JD. Performance modeling and optimization for single- and multi-wall carbon nanotube interconnects Proceedings - Design Automation Conference. 568-573. DOI: 10.1109/DAC.2007.375228  1
2007 Sarvari R, Naeemi A, Zarkesh-Ha P, Meindl JD. Design and optimization for nanoscale power distribution networks in gigascale systems Proceedings of the Ieee 2007 International Interconnect Technology Conference - Digest of Technical Papers. 190-192.  1
2006 Naeemi A, Meindl JD. Compact physical models for multiwall carbon-nanotube interconnects Ieee Electron Device Letters. 27: 338-340. DOI: 10.1109/Led.2006.873765  1
2006 Naeemi A, Sarvari R, Meindl JD. On-chip interconnect networks at the end of the roadmap: Limits and nanotechnology opportunities 2006 International Interconnect Technology Conference, Iitc. 221-223. DOI: 10.1109/IITC.2006.1648693  1
2005 Mule AV, Villalaz RA, Joseph PJ, Naeemi A, Kohl PA, Gaylord TK, Meindl JD. Polylithic integration of electrical and optical interconnect technologies for gigascale fiber-to-the-chip communication Ieee Transactions On Advanced Packaging. 28: 421-433. DOI: 10.1109/Tadvp.2005.847838  1
2005 Naeemi A, Meindl JD. Monolayer metallic nanotube interconnects: Promising candidates for short local interconnects Ieee Electron Device Letters. 26: 544-546. DOI: 10.1109/Led.2005.852744  1
2005 Naeemi A, Meindl JD. Impact of electron-phonon scattering on the performance of carbon nanotube interconnects for GSI Ieee Electron Device Letters. 26: 476-478. DOI: 10.1109/Led.2005.851130  1
2005 Naeemi A, Sarvari R, Meindl JD. Performance comparison between carbon nanotube and copper interconnects for gigascale integration (GSI) Ieee Electron Device Letters. 26: 84-86. DOI: 10.1109/Led.2004.841440  1
2005 Sarvari R, Naeemi A, Venkatesan R, Meindl JD. Impact of size effects on the resistivity of copper wires and consequently the design and performance of metal interconnect networks Proceedings of the Ieee 2005 International Interconnect Technology Conference, Iitc. 197-199.  1
2005 Huang G, Naeemi A, Meindl JD. Minimizing energy-per-bit for On-board LC transmission lines Proceedings of the Ieee 2005 International Interconnect Technology Conference, Iitc. 77-79.  1
2005 Naeemi A, Meindl JD. Impact of deep sub-ambient cooling on GSI interconnect performance Proceedings of the Ieee 2005 International Interconnect Technology Conference, Iitc. 156-158.  1
2005 Naeemi A, Joshi Y, Fedorov A, Kohl P, Meindl JD. The urgency of deep sub-ambient cooling for gigascale integration 2005 International Conference On Integrated Circuit Design and Technology, Icicdt. 171-174.  1
2004 Naeemi A, Davis JA, Meindl JD. Compact physical models for multilevel interconnect crosstalk in gigascale integration (GSI) Ieee Transactions On Electron Devices. 51: 1902-1912. DOI: 10.1109/Ted.2004.837379  1
2004 Naeemi A, Davis JA, Meindl JD. Analysis and optimization of coplanar RLC lines for GSI global interconnection Ieee Transactions On Electron Devices. 51: 985-994. DOI: 10.1109/Ted.2004.829517  1
2004 Naeemi A, Xu J, Mule AV, Gaylord TK, Meindl JD. Optical and electrical interconnect partition length based on chip-to-chip bandwidth maximization Ieee Photonics Technology Letters. 16: 1221-1223. DOI: 10.1109/Lpt.2004.824623  1
2004 Naeemi A, Sarvari R, Meindl JD. Performance comparison between carbon nanotube and copper interconnects for GSI Technical Digest - International Electron Devices Meeting, Iedm. 699-702.  1
2004 Sarvari R, Naeemi A, Meindl JD. General compact model for bit-rate limit of electrical interconnects considering DC resistance, skin effect and surface scattering Proceedings of the Ieee 2004 International Interconnect Technology Conference. 163-165.  1
2004 Naeemi A, Meindl JD. An upper limit for aggregate I/O interconnect bandwidth of GSI chips constrained by power dissipation Proceedings of the Ieee 2004 International Interconnect Technology Conference. 157-159.  1
2003 Naeemi A, Venkatesan R, Meindl JD. Optimal global interconnects for GSI Ieee Transactions On Electron Devices. 50: 980-987. DOI: 10.1109/Ted.2003.812104  1
2003 Naeemi A, Davis JA, Meindl JD. Compact physical models for multilevel interconnect crosstalk in a gigascale SoC Proceedings - Ieee International Soc Conference, Socc 2003. 199-202. DOI: 10.1109/SOC.2003.1241492  1
2003 Naeemi A, Mule AV, Meindl JD. Partition length between board-level electrical and optical interconnects Proceedings of the Ieee 2003 International Interconnect Technology Conference, Iitc 2003. 230-232. DOI: 10.1109/IITC.2003.1219762  1
2002 Mule AV, Naeemi A, Glytsis EN, Gaylord TK, Meindl JD. Towards a comparison between chip-level optical interconnection and board-level exterconnection Proceedings of the Ieee 2002 International Interconnect Technology Conference, Iitc 2002. 92-94. DOI: 10.1109/IITC.2002.1014898  1
2002 Naeemi A, Venkatesan R, Meindl JD. System-on-a-chip global interconnect optimization Proceedings of the Annual Ieee International Asic Conference and Exhibit. 2002: 399-403. DOI: 10.1109/ASIC.2002.1158092  1
2002 Naeemi A, Davis JA, Meindl JD. Optimal global interconnecting devices for GSI Technical Digest - International Electron Devices Meeting. 319-322.  1
2001 Meindl JD, Venkatesan R, Davis JA, Joyner J, Naeemi A, Zarkesh-Ha P, Bakir M, Mulé T, Kohl PA, Martin KP. Interconnecting device opportunities for gigascale integration (GSI) Technical Digest - International Electron Devices Meeting. 525-528.  1
2001 Naeemi A, Davis JA, Meindl JD. Analytical models for coupled distributed RLC lines with ideal and non-ideal return paths Technical Digest - International Electron Devices Meeting. 689-692.  1
2001 Naeemi A, Patel CS, Bakir MS, Zarkesh-Ha P, Martin KP, Meindl JD. Sea of leads: A disruptive paradigm for a system-on-a-chip (SoC) Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 280-281.  1
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